JP2747112B2 - High frequency hybrid integrated circuit device - Google Patents
High frequency hybrid integrated circuit deviceInfo
- Publication number
- JP2747112B2 JP2747112B2 JP2327749A JP32774990A JP2747112B2 JP 2747112 B2 JP2747112 B2 JP 2747112B2 JP 2327749 A JP2327749 A JP 2327749A JP 32774990 A JP32774990 A JP 32774990A JP 2747112 B2 JP2747112 B2 JP 2747112B2
- Authority
- JP
- Japan
- Prior art keywords
- signal conductor
- film
- frequency
- signal
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Waveguide Connection Structure (AREA)
- Non-Reversible Transmitting Devices (AREA)
- Waveguides (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高周波用混成集積回路装置に関し、特にその
発振防止回路の構造に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency hybrid integrated circuit device, and more particularly to a structure of an oscillation preventing circuit thereof.
第４図および第５図はそれぞれ従来の高周波用混成集
積回路装置の発振防止回路の断面構造図を示す。前者は
発振径路の信号導体膜１の一部を分離して帰還量減衰用
の下地抵抗膜２を中間に挿入した構造のものであり、ま
た、後者は同じく一部を分離した信号導体膜１の間に帰
還量減衰用のチップ抵抗２′を導体線または導体テープ
などの接続導体５で接続した構造のものである。ここ
で、３および４は導電体基板および接地導体を、また、
１′および３′は信号導体膜片およびチップ抵抗搭載用
の誘電体基板をそれぞれ示す。FIGS. 4 and 5 are cross-sectional structural views of a conventional oscillation preventing circuit of a high frequency hybrid integrated circuit device. The former has a structure in which a part of the signal conductor film 1 of the oscillation path is separated and a base resistance film 2 for attenuating the feedback amount is inserted in the middle, and the latter has a structure in which the signal conductor film 1 is also partially separated. In this structure, a chip resistor 2 'for attenuating the amount of feedback is connected by a connection conductor 5 such as a conductor wire or a conductor tape. Here, 3 and 4 are a conductor substrate and a ground conductor,
Reference numerals 1 'and 3' denote a signal conductor film piece and a dielectric substrate for mounting a chip resistor, respectively.
しかしながら、上述した従来の高周波用混成集積回路
装置は、高周波信号線路は直流バイアス供給線として共
用する場合が多く、抵抗膜にも高周波成分の外に直流バ
イアス電流が常時流れている場合が多い。従って、この
構造の発振防止回路は目的とする高周波成分の減衰のみ
でなく、直流バイアスも低下させるという欠点を有す
る。However, in the above-described conventional high-frequency hybrid integrated circuit device, the high-frequency signal line is often shared as a DC bias supply line, and a DC bias current always flows outside the high-frequency component in the resistive film in many cases. Therefore, the oscillation preventing circuit having this structure has a drawback that not only the attenuation of the desired high-frequency component but also the DC bias is reduced.
本発明の目的は、上記の情況に鑑み、直流バイアスを
低下させる従来発振防止用回路の欠点を解決した高周波
用混成集積回路装置を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a high-frequency hybrid integrated circuit device which solves the drawbacks of the conventional oscillation preventing circuit for reducing the DC bias in view of the above situation.
本発明によれば、高周波用混成集積回路装置は、誘電
体基板と、前記誘電体基板の一主面に形成される信号導
体膜と、該信号導体膜と高周波信号線路を構成する前記
誘電体基板裏面上の接地導体とを含み、前記高周波信号
線路の発振径路には前記信号導体の一部切除領域と、前
記信号導体の一部切除領域上に露出する下地抵抗膜と、
前記信号導体の一部切除領域上の互いに離間する２つの
信号導体間を端部中央部で接続する前記下地抵抗膜のバ
イパス導電路とからなる発振防止回路が形成されること
を備えて構成される。According to the present invention, the high-frequency hybrid integrated circuit device includes a dielectric substrate, a signal conductor film formed on one main surface of the dielectric substrate, and the dielectric material forming the signal conductor film and the high-frequency signal line. A ground conductor on the back surface of the substrate, the oscillation path of the high-frequency signal line, a partially cut region of the signal conductor, a base resistance film exposed on the partially cut region of the signal conductor,
An oscillation prevention circuit comprising a bypass conductive path of the base resistive film that connects two signal conductors separated from each other on a partially cut region of the signal conductor at an end center portion is formed. You.
本発明によれば、直流バイアス電流は、信号導体膜の
両端中央部に設けられた下地抵抗膜に対するバイパス導
電路を介し、ほとんど減衰を受けることなく通過でき、
他方、発振に寄与する高周波成分のみが抵抗膜を通り減
衰せしめられるので、直流バイアスを低下させることな
き発振防止回路が構成される。According to the present invention, the DC bias current can pass through the bypass conductive path to the underlying resistive film provided at the center of both ends of the signal conductor film with almost no attenuation,
On the other hand, only high-frequency components contributing to oscillation are attenuated through the resistive film, so that an oscillation preventing circuit without lowering the DC bias is configured.
次に、本発明について図面を参照して詳細に説明す
る。Next, the present invention will be described in detail with reference to the drawings.
第１図（ａ）および（ｂ）はそれぞれ本発明の一実施
例を示す発振防止回路の平面図およびそのＸ−Ｘ′断面
図である。本実施例によれば、発振防止回路は、従来と
同じく誘電体基板３上に形成される発振径路の信号導体
膜１の一部を分離し下部の抵抗膜を露出させることによ
って、帰還量減衰用の下地抵抗膜２を信号導体膜１間に
挿入すると共に、更にこの分離した信号導体膜１の端部
の中央部を接続導体５で架橋接続することによって形成
される。1 (a) and 1 (b) are a plan view and a sectional view taken along line XX 'of an oscillation preventing circuit showing an embodiment of the present invention, respectively. According to the present embodiment, the oscillation preventing circuit separates a part of the signal conductor film 1 of the oscillation path formed on the dielectric substrate 3 and exposes the lower resistive film as in the prior art, thereby reducing the feedback amount. The base resistor film 2 for use is inserted between the signal conductor films 1, and the center of the separated end portion of the signal conductor film 1 is further cross-linked by a connection conductor 5.
一般に良く知られているように、導体膜中の高周波電
流は導体膜の縁端部に沿うように分布し、中央部にはほ
とんど流れない性質をもつ。従って、上記実施例の信号
導体膜１内の高周波電流も当然これと全く同じ電流分布
を示す。As is generally well known, the high-frequency current in the conductor film is distributed along the edge of the conductor film, and hardly flows in the center. Therefore, the high-frequency current in the signal conductor film 1 of the above embodiment naturally shows exactly the same current distribution.
第２図は上記実施例における信号導体膜の高周波電流
分布を接地導体の高周波電流分布と共に示す第１図
（ａ）のＹ−Ｙ′断面図である。すなわち、信号導体膜
１の膜幅Ｗの中央部を高周波電流軸ｉの原点（ｘ＝０）
にとると、信号導体膜１を流れる高周波電流ｉ1は原点
（ｘ＝０）で最小となり、縁端部（ｘ＝W/2,−W/2）で
最大となる。このとき接地導体４上の高周波電流ｉ2は
当然のことながらこれとは全く逆となる。FIG. 2 is a sectional view taken along the line YY 'of FIG. 1 (a) showing the high-frequency current distribution of the signal conductor film in the above embodiment together with the high-frequency current distribution of the ground conductor. That is, the center of the film width W of the signal conductor film 1 is defined as the origin (x = 0) of the high-frequency current axis i.
, The high-frequency current i 1 flowing through the signal conductor film 1 becomes minimum at the origin (x = 0) and becomes maximum at the edge (x = W / 2, −W / 2). At this time, the high-frequency current i 2 on the ground conductor 4 is, of course, completely opposite to this.
従って、分離した信号導体膜１の両端中央部を架橋接
続した接続導体５には高周波電流はほとんど通らないこ
ととなり、言わば直流バイアス電流のためのバイパス導
電路としてのみ機能し得るようになる。すなわち、高周
波電流および直流バイアス電流の双方に対してそれぞれ
独立の通過路が形成されるので、直流バイアスを低下さ
せることなき発振防止回路として機能することができ
る。Therefore, the high-frequency current hardly passes through the connection conductor 5 in which the center portions of both ends of the separated signal conductor film 1 are cross-linked, so that it can function only as a bypass conductive path for a DC bias current. That is, since independent passages are formed for both the high-frequency current and the DC bias current, the circuit can function as an oscillation preventing circuit without reducing the DC bias.
第３図（ａ）および（ｂ）はそれぞれ本発明の他の実
施例を示す発振防止回路の平面図およびそのＹ−Ｙ′断
面図である。本実施例によれば、信号導体膜１の一部
は、高周波電流の最も流れにくい中央部のみを残して下
地抵抗膜２上から切除される。本実施例では残された信
号導体膜１の中央部が直流バイアス電流のバイパス導体
として機能する。この回路構造は前記実施例に比べ、組
立の接続工数を低減できる利点がある。3 (a) and 3 (b) are a plan view and a YY 'sectional view of an oscillation preventing circuit showing another embodiment of the present invention, respectively. According to the present embodiment, a part of the signal conductor film 1 is cut off from above the base resistance film 2 except for the central portion where the high-frequency current hardly flows. In the present embodiment, the central portion of the remaining signal conductor film 1 functions as a bypass conductor for the DC bias current. This circuit structure has an advantage that the number of connection steps for assembly can be reduced as compared with the above embodiment.
以上詳細に説明したように、本発明によれば、発振径
路の帰還量減衰用の下地抵抗膜に対するバイパス導電路
が高周波電流分布の最も少ない両端中央部を結んで設け
られるので、抵抗膜上の高周波電流の流れに対しほとん
ど影響を与えることなく、所要の直流バイアス直流をこ
のバイパス導電路を介し全く独立に流すことができる。
従って、従来の如く直流バイアス機能を低下させること
なき発振防止用回路を備えた高周波用混成集積回路装置
を容易に実現することができる。As described in detail above, according to the present invention, since the bypass conductive path to the base resistance film for attenuating the feedback amount of the oscillation path is provided by connecting the center portions at both ends where the high-frequency current distribution is the least, the bypass path is provided on the resistance film. The required DC bias DC can be flowed completely independently through this bypass conductive path with little effect on the flow of the high frequency current.
Therefore, it is possible to easily realize a high-frequency hybrid integrated circuit device including a circuit for preventing oscillation without lowering the DC bias function as in the related art.
第１図（ａ）および（ｂ）はそれぞれ本発明の一実施例
を示す発振防止回路の平面図およびそのＸ−Ｘ′断面
図、第２図は上記実施例における信号導体膜の高周波電
流分布を接地導体の高周波電流分布と共に示す第１図
（ａ）のＹ−Ｙ′断面図、第３図（ａ）および（ｂ）は
それぞれ本発明の他の実施例を示す発振防止回路の平面
図およびそのＹ−Ｙ′断面図、第４図および第５図はそ
れぞれ従来の高周波混成集積回路装置の発振防止回路の
断面構造図である。 １……信号導体膜、２……（帰還量減衰用の）下地抵抗
膜、３……誘電体基板、４……接地導体、５……接続導
体。1 (a) and 1 (b) are a plan view and an XX 'sectional view of an oscillation preventing circuit showing an embodiment of the present invention, respectively, and FIG. 2 is a high-frequency current distribution of a signal conductor film in the above embodiment. FIG. 1 (a) is a cross-sectional view taken along the line YY 'of FIG. 1 (a), and FIGS. 3 (a) and 3 (b) are plan views of an oscillation preventing circuit showing another embodiment of the present invention. 4 and 5 are cross-sectional structural views of an oscillation preventing circuit of a conventional high frequency hybrid integrated circuit device. 1 ... signal conductor film, 2 ... underlying resistive film (for attenuating feedback amount), 3 ... dielectric substrate, 4 ... ground conductor, 5 ... connection conductor.
Claims (1)
形成される信号導体膜と、該信号導体膜と高周波信号線
路を構成する前記誘電体基板裏面上の接地導体とを含
み、前記高周波信号線路の発振径路には前記信号導体の
一部切除領域と、前記信号導体の一部切除領域上に露出
する下地抵抗膜と、前記信号導体の一部切除領域上の互
いに離間する２つの信号導体間を端部中央部で接続する
前記下地抵抗膜のバイパス導電路とからなる発振防止回
路が形成されることを特徴とする高周波用混成集積回路
装置。1. A semiconductor device comprising: a dielectric substrate; a signal conductor film formed on one main surface of the dielectric substrate; and a ground conductor on the back surface of the dielectric substrate forming the signal conductor film and a high-frequency signal line. In the oscillation path of the high-frequency signal line, a partly cut region of the signal conductor, a base resistive film exposed on the partly cut region of the signal conductor, and a part of the signal conductor separated from each other on the partly cut region of the signal conductor A high-frequency hybrid integrated circuit device, wherein an oscillation preventing circuit comprising a bypass conductive path of the base resistive film connecting two signal conductors at a center portion at an end is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2327749A JP2747112B2 (en) | 1990-11-27 | 1990-11-27 | High frequency hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2327749A JP2747112B2 (en) | 1990-11-27 | 1990-11-27 | High frequency hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04192902A JPH04192902A (en) | 1992-07-13 |
| JP2747112B2 true JP2747112B2 (en) | 1998-05-06 |
Family
ID=18202555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2327749A Expired - Fee Related JP2747112B2 (en) | 1990-11-27 | 1990-11-27 | High frequency hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2747112B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3723202B2 (en) * | 2002-08-01 | 2005-12-07 | 松下電器産業株式会社 | Transmission line and semiconductor integrated circuit device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5797201A (en) * | 1980-12-09 | 1982-06-16 | Fujitsu Ltd | Integrated circuit for microwave |
| JPS5952901A (en) * | 1982-09-18 | 1984-03-27 | Mitsubishi Electric Corp | Microstrip line circuit device |
| JPS60206202A (en) * | 1984-03-30 | 1985-10-17 | Toshiba Corp | Bias pattern of microwave circuit |
| JPH02166803A (en) * | 1988-12-20 | 1990-06-27 | Matsushita Electric Ind Co Ltd | Microwave integrated circuit |
-
1990
- 1990-11-27 JP JP2327749A patent/JP2747112B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04192902A (en) | 1992-07-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |