JPH0529490A - Circuit board for mounting semiconductor - Google Patents
Circuit board for mounting semiconductorInfo
- Publication number
- JPH0529490A JPH0529490A JP20614691A JP20614691A JPH0529490A JP H0529490 A JPH0529490 A JP H0529490A JP 20614691 A JP20614691 A JP 20614691A JP 20614691 A JP20614691 A JP 20614691A JP H0529490 A JPH0529490 A JP H0529490A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- foil
- circuit board
- copper
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、絶縁層に接するアルミ
ニウム−銅クラッド箔の箔足を規定する事によりピール
強度と耐電圧性能が向上し、電気機器、通信機、および
自動車等に用いられる半導体搭載用回路基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention improves peel strength and withstand voltage performance by defining a foil foot of an aluminum-copper clad foil in contact with an insulating layer, and is used for electric equipment, communication equipment, automobiles and the like. The present invention relates to a semiconductor mounting circuit board.
【０００２】[0002]
【従来の技術】従来、回路基板の回路に用いられる導電
箔としては、銅箔、ニッケルメッキ付き銅箔およびアル
ミニウム−銅クラッド箔が知られている。そして、これ
ら導電箔には箔足の規定が特になされていなかった。2. Description of the Related Art Conventionally, copper foil, nickel-plated copper foil and aluminum-copper clad foil have been known as conductive foils used for circuits of circuit boards. In addition, no regulation of foil foot is made on these conductive foils.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、近年、
半導体搭載用回路基板は高密度実装化が進み、さらに、
パワーモジュール用途などでは高耐電圧性能や高ピール
強度を有する回路基板が要求されるにともない、絶縁層
と導電箔との信頼性が問題となっている。However, in recent years,
The circuit boards for mounting semiconductors are becoming more densely packaged.
With the demand for circuit boards having high withstand voltage performance and high peel strength for power module applications and the like, reliability between the insulating layer and the conductive foil has become a problem.
【０００４】本発明は、かかる問題点を解決したもので
あり、回路基板に用いる絶縁層と接着するアルミニウム
−銅クラッド箔の箔足を規定することにより、回路基板
としての高耐電圧性能および高ピール強度を保持する事
を見い出し、本発明を完成するに至った。The present invention solves such a problem, and by defining a foil foot of an aluminum-copper clad foil that adheres to an insulating layer used for a circuit board, high withstand voltage performance and high performance as a circuit board are obtained. It was found that the peel strength was maintained, and the present invention was completed.
【０００５】[0005]
【課題を解決するための手段】すなわち、本発明は金属
基板に絶縁層を介してアルミニウム−銅クラッド箔を積
層してなる回路基板において、前記絶縁層に接する前記
アルミニウム−銅クラッド箔の箔足が0.5μｍ〜50μｍ
であることを特徴とする半導体搭載用回路基板である。That is, according to the present invention, in a circuit board formed by laminating an aluminum-copper clad foil on a metal substrate via an insulating layer, a foil foot of the aluminum-copper clad foil contacting the insulating layer is provided. 0.5 μm to 50 μm
Is a circuit board for mounting semiconductors.
【０００６】[0006]
【作用および実施例】以下、図面により本発明を詳細に
説明する。図１は、本発明で用いられる回路基板の断面
図である。図１は、ベース金属基板１に絶縁層２を介し
て規定の箔足４を有するアルミニウムー銅クラッド箔３
のアルミニウム箔５面を上面として積層したものであ
る。また、図２は、絶縁層２に積層するアルミニウムー
銅クラッド箔３の銅箔６面を上面とした回路基板の断面
図を示した。図３は、本発明の回路基板に半導体等を実
装した半導体搭載回路の断面図である。さらに、図４及
び図５は、箔足の長さに対する絶縁破壊強度とピール強
度との関係を示すものである。The present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view of a circuit board used in the present invention. FIG. 1 shows an aluminum-copper clad foil 3 having a prescribed metal foot 4 on a base metal substrate 1 with an insulating layer 2 interposed therebetween.
The aluminum foil 5 is laminated as the upper surface. Further, FIG. 2 shows a cross-sectional view of the circuit board with the copper foil 6 surface of the aluminum-copper clad foil 3 laminated on the insulating layer 2 as the top surface. FIG. 3 is a sectional view of a semiconductor-mounted circuit in which a semiconductor or the like is mounted on the circuit board of the present invention. 4 and 5 show the relationship between the dielectric breakdown strength and the peel strength with respect to the length of the foil foot.
【０００７】本発明の回路基板に用いるベース金属基板
１としては、良熱伝導性を持つアルミニウムおよびアル
ミニウム合金、銅および銅合金、鉄、並びにステンレス
等が使用可能である。また、ベース金属基板１の厚みと
しては、特に制限はないが0.5 ｍｍ〜3.0 ｍｍが一般に
用いられる。As the base metal substrate 1 used for the circuit board of the present invention, aluminum and aluminum alloys, copper and copper alloys, iron, stainless steel and the like having good thermal conductivity can be used. The thickness of the base metal substrate 1 is not particularly limited, but 0.5 mm to 3.0 mm is generally used.
【０００８】また、本発明に使用される絶縁層２として
は、各種セラミックス、無機フィラーを含有した高分子
樹脂絶縁層、ガラス繊維を含有する高分子樹脂層および
耐熱性高分子樹脂絶縁層が用いられる。また、その絶縁
層２の肉厚は、絶縁不良を生じない程度で有れば特に制
限はなく、20μｍ以上が一般に使用される。絶縁層２に
用いる無機粉体としてはアルミナ、シリカ、ベリリヤ、
ボロンナイトライド、マグネシア、窒化珪素、窒化アル
ミニウムおよび炭化珪素等が用いられ、高分子樹脂とし
ては、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂
および各種エンジニアプラスチックが使用できる。As the insulating layer 2 used in the present invention, various ceramics, a polymer resin insulating layer containing an inorganic filler, a polymer resin layer containing a glass fiber and a heat resistant polymer resin insulating layer are used. Be done. The thickness of the insulating layer 2 is not particularly limited as long as it does not cause insulation failure, and 20 μm or more is generally used. As the inorganic powder used for the insulating layer 2, alumina, silica, beryllia,
Boron nitride, magnesia, silicon nitride, aluminum nitride, silicon carbide and the like are used, and as the polymer resin, epoxy resin, phenol resin, polyimide resin and various engineered plastics can be used.
【０００９】本発明に用いられるアルミニウム−銅クラ
ッド箔３の材質としては、純アルミニウムおよびアルミ
ニウム合金でもかまわない。また、アルミニウムと銅の
接合方法としては、圧延法でもメッキ法でも差し支えな
い。また、メッキ法の場合は、アルミニウムと銅との接
合強度を上げるために、アルミニウムと銅の間に亜鉛、
錫およびニッケル等をメッキすることもできる。The aluminum-copper clad foil 3 used in the present invention may be made of pure aluminum or aluminum alloy. Further, the method of joining aluminum and copper may be a rolling method or a plating method. Further, in the case of the plating method, in order to increase the bonding strength between aluminum and copper, zinc between aluminum and copper,
It is also possible to plate tin and nickel or the like.
【００１０】また、本発明のアルミニウム−銅クラッド
箔３は、厚みを特定するものではないが、例えば大電流
用途では、35μｍ〜1,000 μｍが好ましく、制御用の小
電流では、9 μｍ〜70μｍの箔厚が望ましい。The thickness of the aluminum-copper clad foil 3 of the present invention is not specified, but 35 μm to 1,000 μm is preferable for high current applications, and 9 μm to 70 μm for small currents for control. Foil thickness is desirable.
【００１１】本発明で使用されるアルミニウムー銅クラ
ッド箔３の箔足とは、接着面に対する箔の粗面程度を示
すものであり、その長さは、0.5μｍ〜50μｍである。
箔足４が0.5 μｍ未満では絶縁層２との接着強度が弱
く、アルミニウム−銅クラッド箔３が簡単に剥がれてし
まう。また、50μｍを越えると箔足の先端で電界集中が
生じ、耐電圧性能が著しく低下してしまう。The foil foot of the aluminum-copper clad foil 3 used in the present invention indicates the degree of the rough surface of the foil with respect to the adhesive surface, and the length thereof is 0.5 μm to 50 μm.
If the foil foot 4 is less than 0.5 μm, the adhesive strength with the insulating layer 2 is weak and the aluminum-copper clad foil 3 is easily peeled off. On the other hand, when the thickness exceeds 50 μm, electric field concentration occurs at the tip of the foil foot, and the withstand voltage performance is significantly deteriorated.
【００１２】また、高ピール強度を必要とする分野で
は、アルミニウム−銅クラッド箔３の箔足４が10〜50μ
ｍが好ましく、高耐電圧性能を必要とする分野では、箔
足４が0.5 μｍ〜20μｍが好ましい。また、ピール強度
と耐電圧性能をともに必要とする用途では、箔足４が10
μｍ〜20μｍであることが好ましい。Further, in the field requiring high peel strength, the foil foot 4 of the aluminum-copper clad foil 3 has a thickness of 10 to 50 μm.
m is preferable, and in the field where high withstand voltage performance is required, the thickness of the foil foot 4 is preferably 0.5 μm to 20 μm. In addition, for applications that require both peel strength and withstand voltage performance,
The thickness is preferably 20 μm to 20 μm.
【００１３】実施例１ 図３には、ベース金属基板１として厚さ1.5 ｍｍのアル
ミニウム基板上に、絶縁層２となるシリカ含有エポキシ
樹脂を100 μｍの厚みで塗布し、アルミニウム40μｍ−
銅85μｍのクラッド箔３をアルミニウム箔５面を上面と
して張り合わせた回路基板を用い、半導体等を実装した
半導体搭載回路の断面図である。箔足の長さは15μｍの
ものを用いた。まづ図１に示した構成の回路構成用基板
（アルミニウム基板；厚さ1.5 ｍｍ、絶縁層；厚さ100
μｍ、アルミニウム−銅クラッド箔；厚さ40μｍ−85μ
ｍ）にスクリーン印刷法でレジストを塗布し、アルミニ
ウム−銅クラッド箔３の両者に対しエッチング可能な塩
化第二鉄等でエッチングして配線回路を形成させる。レ
ジストを取り除いた後、アルミニウムパッドが必要な部
分に再びレジスト塗布し、アルカリエッチング等の選択
的にアルミニウムを溶かすエッチング液を用いて不必要
なアルミニウム部分を取り除き、銅箔部を露出させる。
レジストを取り除いた後、該銅導電回路８上に半田７を
介して半導体やチップ抵抗等を搭載した後、半導体１１
とアルミニウムパッド９とをアルミニウムリード線から
なるワイヤー１０により超音波振動法で固着したもので
ある。Example 1 In FIG. 3, a silica metal-containing epoxy resin to be an insulating layer 2 was applied to an aluminum substrate having a thickness of 1.5 mm as a base metal substrate 1 to a thickness of 100 μm, and aluminum 40 μm-
FIG. 6 is a cross-sectional view of a semiconductor-mounted circuit in which a semiconductor or the like is mounted using a circuit board in which a clad foil 3 of copper 85 μm is bonded with an aluminum foil 5 surface as an upper surface. The length of the foil foot was 15 μm. First, the circuit configuration substrate having the configuration shown in FIG. 1 (aluminum substrate; thickness 1.5 mm, insulating layer; thickness 100)
μm, aluminum-copper clad foil; thickness 40 μm-85 μ
A resist is applied to m) by a screen printing method, and both of the aluminum-copper clad foil 3 are etched with ferric chloride or the like that can be etched to form a wiring circuit. After removing the resist, the portion where the aluminum pad is required is coated again with the resist, and the unnecessary aluminum portion is removed by using an etching solution such as alkali etching that selectively dissolves aluminum to expose the copper foil portion.
After removing the resist, a semiconductor, a chip resistor and the like are mounted on the copper conductive circuit 8 via the solder 7, and then the semiconductor 11
The aluminum pad 9 and the aluminum pad 9 are fixed to each other by an ultrasonic vibration method with a wire 10 made of an aluminum lead wire.
【００１４】実施例２ 図４は、ベース金属基板１として厚さ1.5 ｍｍのアルミ
ニウム基板上に、絶縁層２としてシリカ含有エポキシ樹
脂を100 μｍの厚みで塗布し、アルミニウム40μｍ−銅
300 μｍのクラッド箔３を銅箔６面を上面として張り合
わせた回路基板を用い、箔足の長さと耐電圧性能（絶縁
破壊強度）との関係を示した図である。絶縁破壊測定は
JIS C-2110に基づき、TOS 8700形（菊水電子工業（株）
を用いて行った。Example 2 In FIG. 4, a silica metal-containing epoxy resin was applied as an insulating layer 2 to a thickness of 100 μm on an aluminum substrate having a thickness of 1.5 mm as a base metal substrate 1 to obtain aluminum 40 μm-copper.
FIG. 3 is a diagram showing the relationship between the length of a foil leg and the withstand voltage performance (dielectric breakdown strength) using a circuit board obtained by laminating a 300 μm clad foil 3 with the copper foil 6 surface as the upper surface. Dielectric breakdown measurement
Based on JIS C-2110, TOS 8700 type (Kikusui Electronics Co., Ltd.)
Was carried out.
【００１５】実施例３ 図５は、ベース金属基板１として厚さ1.5 ｍｍのアルミ
ニウム基板上に、絶縁層２としてシリカ含有エポキシ樹
脂を100 μｍの厚みで塗布し、アルミニウム40μｍ−銅
85μｍのクラッド箔３をアルミニウム箔５面を上面とし
張り合わせた回路基板を用い、箔足の長さとピール強度
との関係を示した図である。ピール強度はJIS C-6481に
基づき、テンシロンU-1160（東洋ボールドウィン（株）
を用い行った。Example 3 In FIG. 5, a silica metal-containing epoxy resin is applied as an insulating layer 2 to a thickness of 100 μm on an aluminum substrate having a thickness of 1.5 mm as a base metal substrate 1, and aluminum 40 μm-copper is used.
It is the figure which showed the relationship between the length of a foil leg and peel strength using the circuit board which stuck the clad foil 3 of 85 micrometers to the aluminum foil 5 side as the upper surface. Peel strength is based on JIS C-6481, Tensilon U-1160 (Toyo Baldwin Co., Ltd.)
Was performed.
【００１６】[0016]
【発明の効果】以上のとおり本発明は、アルミニウム−
銅クラッド箔の箔足の長さを規定する事により、高ピー
ル強度及び／または高耐電圧性能を有する回路基板を作
製する事が可能となった。As described above, the present invention is made of aluminum-
By defining the length of the copper clad foil, it has become possible to produce a circuit board having high peel strength and / or high withstand voltage performance.
【図１】本発明の回路基板でアルミニウム−銅クラッド
箔のアルミニウム箔を上面とした断面図である。FIG. 1 is a cross-sectional view of a circuit board of the present invention with an aluminum foil of an aluminum-copper clad foil as an upper surface.
【図２】本発明の回路基板でアルミニウム−銅クラッド
箔の銅箔を上面とした断面図である。FIG. 2 is a cross-sectional view of a circuit board of the present invention with a copper foil of an aluminum-copper clad foil as an upper surface.
【図３】本発明の回路基板に導電回路を形成し、半導体
等を実装した半導体搭載回路の断面図である。FIG. 3 is a cross-sectional view of a semiconductor-mounted circuit in which a conductive circuit is formed on the circuit board of the present invention and a semiconductor or the like is mounted.
【図４】本発明のアルミニウム−銅クラッド箔の箔足の
長さと絶縁破壊強度との関係を示したものである。FIG. 4 is a graph showing the relationship between the length of foil legs and the dielectric breakdown strength of the aluminum-copper clad foil of the present invention.
【図５】本発明のアルミニウム−銅クラッド箔の箔足の
長さとピール強度との関係を示したものである。FIG. 5 shows the relationship between the foil foot length and the peel strength of the aluminum-copper clad foil of the present invention.
１ ベース金属基板 ２ 絶縁層 ３ アルミニウム−銅クラッド箔 ４ 箔足 ５ アルミニウム箔 ６ 銅箔 ７ 半田 ８ 銅導電回路 ９ アルミニウムパッド １０ ワイヤー １１ 半導体 1 Base Metal Substrate 2 Insulating Layer 3 Aluminum-Copper Clad Foil 4 Foil Feet 5 Aluminum Foil 6 Copper Foil 7 Solder 8 Copper Conductive Circuit 9 Aluminum Pad 10 Wire 11 Semiconductor
【手続補正書】[Procedure amendment]
【提出日】平成４年７月３日[Submission date] July 3, 1992
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１３[Correction target item name] 0013
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１３】 実施例１ 図３には、ベース金属基板１として厚さ1.5 ｍｍのアル
ミニウム基板上に、絶縁層２となるシリカ含有エポキシ
樹脂を100 μｍの厚みで塗布し、アルミニウム40μｍ−
銅85μｍのクラッド箔３をアルミニウム箔５面を上面と
して張り合わせた回路基板を用い、半導体等を実装した
半導体搭載回路の断面図である。箔足の長さはＲz で15
μｍのものを用いた。まづ図１に示した構成の回路構成
用基板（アルミニウム基板；厚さ1.5ｍｍ、絶縁層；厚
さ100 μｍ、アルミニウム−銅クラッド箔；厚さ40μｍ
−85μｍ）にスクリーン印刷法でレジストを塗布し、ア
ルミニウム−銅クラッド箔３の両者に対しエッチング可
能な塩化第二鉄等でエッチングして配線回路を形成させ
る。レジストを取り除いた後、アルミニウムパッドが必
要な部分に再びレジスト塗布し、アルカリエッチング等
の選択的にアルミニウムを溶かすエッチング液を用いて
不必要なアルミニウム部分を取り除き、銅箔部を露出さ
せる。レジストを取り除いた後、該銅導電回路８上に半
田７を介して半導体やチップ抵抗等を搭載した後、半導
体１１とアルミニウムパッド９とをアルミニウムリード
線からなるワイヤー１０により超音波振動法で固着した
ものである。Example 1 In FIG. 3, a silica metal-containing epoxy resin to be the insulating layer 2 is applied to a thickness of 100 μm on an aluminum substrate having a thickness of 1.5 mm as a base metal substrate 1, and aluminum 40 μm-
FIG. 6 is a cross-sectional view of a semiconductor-mounted circuit in which a semiconductor or the like is mounted using a circuit board in which a clad foil 3 of copper 85 μm is bonded with an aluminum foil 5 surface as an upper surface. Foil foot length is Rz 15
The thing with a micrometer was used. First, the circuit configuration substrate having the configuration shown in FIG. 1 (aluminum substrate; thickness 1.5 mm, insulating layer; thickness 100 μm, aluminum-copper clad foil; thickness 40 μm)
-85 μm) is coated with a resist by a screen printing method, and both of the aluminum-copper clad foil 3 are etched with ferric chloride or the like that can be etched to form a wiring circuit. After removing the resist, the resist is again applied to the portion where the aluminum pad is required, and the unnecessary aluminum portion is removed by using an etching solution such as alkali etching that selectively dissolves aluminum to expose the copper foil portion. After removing the resist, a semiconductor, a chip resistor, etc. are mounted on the copper conductive circuit 8 via the solder 7, and then the semiconductor 11 and the aluminum pad 9 are fixed by the ultrasonic vibration method with the wire 10 made of an aluminum lead wire. It was done.
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１４[Correction target item name] 0014
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１４】 実施例２ 図４は、ベース金属基板１として厚さ1.5 ｍｍのアルミ
ニウム基板上に、絶縁層２としてシリカ含有エポキシ樹
脂を100 μｍの厚みで塗布し、アルミニウム40μｍ−銅
300 μｍのクラッド箔３を銅箔６面を上面として張り合
わせた回路基板を用い、箔足の長さ（Ｒz ）と耐電圧性
能（絶縁破壊強度）との関係を示した図である。絶縁破
壊測定はJIS C-2110に基づき、TOS 8700形（菊水電子工
業（株）を用いて行った。Example 2 FIG. 4 shows that a silica-containing epoxy resin is applied as an insulating layer 2 in a thickness of 100 μm on an aluminum substrate having a thickness of 1.5 mm as a base metal substrate 1 to obtain aluminum 40 μm-copper.
FIG. 3 is a diagram showing a relationship between a foil leg length (Rz) and a withstand voltage performance (dielectric breakdown strength) by using a circuit board obtained by laminating a 300 μm clad foil 3 with a copper foil 6 surface as an upper surface. Dielectric breakdown measurement was performed using TOS 8700 type (Kikusui Electronics Co., Ltd.) based on JIS C-2110.
【手続補正３】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１５[Correction target item name] 0015
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１５】 実施例３ 図５は、ベース金属基板１として厚さ1.5 ｍｍのアルミ
ニウム基板上に、絶縁層２としてシリカ含有エポキシ樹
脂を100 μｍの厚みで塗布し、アルミニウム40μｍ−銅
85μｍのクラッド箔３をアルミニウム箔５面を上面とし
張り合わせた回路基板を用い、箔足の長さ（Ｒz ）とピ
ール強度との関係を示した図である。ピール強度はJIS
C-6481に基づき、テンシロンU-1160（東洋ボールドウィ
ン（株）を用い行った。Example 3 FIG. 5 shows that a silica metal-containing epoxy resin is applied as an insulating layer 2 in a thickness of 100 μm on an aluminum substrate having a thickness of 1.5 mm as a base metal substrate 1 and aluminum 40 μm-copper
FIG. 3 is a diagram showing the relationship between the length (Rz) of the foil leg and the peel strength using a circuit board in which the clad foil 3 having a thickness of 85 μm is laminated with the surface of the aluminum foil 5 as the upper surface. Peel strength is JIS
Based on C-6481, Tensilon U-1160 (Toyo Baldwin Co., Ltd.) was used.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 1/09 Ｃ 8727−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location H05K 1/09 C 8727-4E
Claims (1)
−銅クラッド箔を積層してなる回路基板において、前記
絶縁層に接する前記アルミニウム−銅クラッド箔の箔足
が0.5 μｍ〜50μｍであることを特徴とする半導体搭載
用回路基板。Claim: What is claimed is: 1. A circuit board comprising a metal substrate and an aluminum-copper clad foil laminated on the metal substrate with an insulating layer interposed therebetween, and the foil leg of the aluminum-copper clad foil in contact with the insulating layer is 0.5 μm. A semiconductor-mounting circuit board having a thickness of up to 50 μm.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20614691A JP3156798B2 (en) | 1991-07-24 | 1991-07-24 | Circuit board for semiconductor mounting |
| SG1996000237A SG54988A1 (en) | 1991-07-24 | 1992-07-23 | Circuit substrate for mounting a semiconductor |
| EP01100741A EP1132961B1 (en) | 1991-07-24 | 1992-07-23 | Method for producing a circuit substrate having a mounted semiconductor element |
| DE69233801T DE69233801D1 (en) | 1991-07-24 | 1992-07-23 | A method of manufacturing a circuit substrate with a mounted semiconductor element |
| EP92112599A EP0525644A1 (en) | 1991-07-24 | 1992-07-23 | Circuit substrate for mounting a semiconductor element |
| US07/917,971 US5362926A (en) | 1991-07-24 | 1992-07-24 | Circuit substrate for mounting a semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20614691A JP3156798B2 (en) | 1991-07-24 | 1991-07-24 | Circuit board for semiconductor mounting |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0529490A true JPH0529490A (en) | 1993-02-05 |
| JP3156798B2 JP3156798B2 (en) | 2001-04-16 |
Family
ID=16518556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20614691A Expired - Lifetime JP3156798B2 (en) | 1991-07-24 | 1991-07-24 | Circuit board for semiconductor mounting |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3156798B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001189401A (en) * | 1999-12-28 | 2001-07-10 | Hitachi Ltd | Wiring board and semiconductor device |
| JP2015053442A (en) * | 2013-09-09 | 2015-03-19 | 三菱電機株式会社 | Semiconductor device |
| JP2015220341A (en) * | 2014-05-19 | 2015-12-07 | 三菱電機株式会社 | Metal base substrate, power module, and manufacturing method of metal base substrate |
| US11724230B2 (en) | 2017-07-07 | 2023-08-15 | Saudi Arabian Oil Company | Multilayer aromatic polyamide thin-film composite membranes for separation of gas mixtures |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5413707B2 (en) | 2005-06-06 | 2014-02-12 | Ｄｏｗａエレクトロニクス株式会社 | Metal-ceramic composite substrate and manufacturing method thereof |
| JP5120653B2 (en) | 2006-04-17 | 2013-01-16 | Ｄｏｗａエレクトロニクス株式会社 | Solder layer, device bonding substrate using the same, and method for manufacturing the device bonding substrate |
| JP5526336B2 (en) | 2007-02-27 | 2014-06-18 | Ｄｏｗａエレクトロニクス株式会社 | Solder layer, device bonding substrate using the same, and manufacturing method thereof |
-
1991
- 1991-07-24 JP JP20614691A patent/JP3156798B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001189401A (en) * | 1999-12-28 | 2001-07-10 | Hitachi Ltd | Wiring board and semiconductor device |
| JP2015053442A (en) * | 2013-09-09 | 2015-03-19 | 三菱電機株式会社 | Semiconductor device |
| JP2015220341A (en) * | 2014-05-19 | 2015-12-07 | 三菱電機株式会社 | Metal base substrate, power module, and manufacturing method of metal base substrate |
| US11724230B2 (en) | 2017-07-07 | 2023-08-15 | Saudi Arabian Oil Company | Multilayer aromatic polyamide thin-film composite membranes for separation of gas mixtures |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3156798B2 (en) | 2001-04-16 |
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