JPH0525814U - Output amplitude limit circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize an output amplitude limiting circuit that can output a large amplitude by using a clamp transistor with low reverse breakdown voltage between the base and emitter. [Structure] The emitter follower output of the _first transistor (Q ₁ , Q ₃ ) is used for the second clamping transistor (Q ₂ ,
Q ₄₎ of the base - drives the scan terminals, base of the second transistor when a reverse bias (Q _2, Q ₄₎ - by following the amplifier stage 2 outputs the ground potential, the clamp transistor (Q
₂ , the reverse voltage between the base emitters of Q ₄ ) is V _BE (about 0.
I tried not to exceed 7V).

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an increase in output amplitude in an output amplitude limiting circuit such as an operational amplifier circuit.

[0002]

[Prior Art]

FIG. 3 is a circuit configuration diagram showing a configuration of an output amplitude limiting circuit in a conventional operational amplifier circuit. In the operational amplifier circuit shown in the above figure, the output voltage V _O of the amplifier stage represented by the current source g _m and the output impedance R _o is the ON voltage of the clamping diodes D ₁ and D ₂ which is V _F. If the high-voltage side clamp voltage is V _CH and the low-voltage side clamp voltage is V _CL , then V _CL −V _F <V _O <V _CH + V _F (1).

[0003]

[Problems to be solved by the device]

However, when the above-mentioned circuit is realized by an IC, a diode-connected transistor is often used instead of the diode. In that case, a reverse voltage is applied between the base and emitter when the transistor does not conduct. The magnitude of this reverse voltage is V _O -V _CL in the case of diode D ₁ , and the reverse voltage also increases as V _O increases. The same applies to the case of the diode D ₂ . If the reverse withstand voltage of V _BE is V _{EBMA X} , the output amplitude of the buffer amplifier 1 is limited to V _EBMAX + V _F. Since the high-speed transistor has V _EBMAX of about 2V, there was a problem that an output amplitude of 2.7V or more could not be output. An object of the present invention is to realize an output amplitude limiting circuit capable of large amplitude output by using a clamp transistor having a low reverse breakdown voltage between the base and the emitter.

[0004]

[Means for Solving the Problems]

 The output amplitude limiting circuit according to the present invention has a first transistor whose base terminal is connected to the output terminal of the amplification stage and whose collector terminal is connected to the voltage source, and one end of which is connected to the emitter terminal of this first transistor. And a resistor whose other end is connected to the clamp voltage, a base terminal is connected to the emitter terminal of the first transistor, a collector terminal is connected to the voltage source, and an emitter terminal is connected to the output terminal of the amplification stage. And two transistors.

[0005]

[Action]

 By driving the base terminal of the second transistor with the emitter follower output of the first transistor, the base potential of the second transistor is made to follow the output of the amplification stage during reverse bias, and the second transistor The reverse breakdown voltage between the base and the emitter was not exceeded.

[0006]

【Example】

 Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration circuit diagram showing an embodiment of an output amplitude limiting circuit according to the present invention.

In the operational amplifier, 2 is an amplification stage, 3 is an output amplitude limiting circuit that limits the output amplitude of the amplification stage 2, and 1 is a buffer amplifier of gain 1 that outputs a signal equal to the output of the output amplitude limiting circuit 3. is there. Here for simplicity, the amplifier stage 2 is equivalently expressed by a current source I _in the output resistance R _o, the output of the amplifier stage 2 is a connection point of the output resistor R _o a current source I _in (hereinafter voltage amplification (Called a node). On the low voltage side of the output amplitude limiting circuit 3, the base terminal of the first NPN transistor Q ₁ is connected to the voltage amplification node N, and the collector terminal is connected to the positive voltage source V _CC . The base terminal of the second NPN transistor Q ₂ is connected to the emitter terminal of the transistor Q ₁ , the collector terminal is connected to the positive voltage source V _CC , and the emitter terminal is connected to the voltage amplification node N. The emitter terminal of the transistor Q ₁ is connected to the low side clamp voltage V _CL via the resistor R ₁ .

Similarly, on the high voltage side of the output amplitude limiting circuit 3, the base terminal of the first PNP transistor Q ₃ is connected to the voltage amplification node N, and the collector terminal is connected to the negative voltage source V _EE. To do. The base terminal of the second PNP transistor Q ₄ is connected to the emitter terminal of the transistor Q ₃ , the collector terminal is connected to the negative voltage source V _EE , and the emitter terminal is connected to the voltage amplification node N. To do. The emitter terminal of the transistor Q ₃ is connected to the high side clamp voltage V _CH via the resistor R ₂ .

The operation of the output amplitude limiting circuit having the above configuration will be described below with reference to FIG. Here, only the operation of the output amplitude limiting circuit 3 on the low voltage side will be described. The high voltage side operates symmetrically with the low voltage side. When the voltage V _o > 0, the emitter potential of the transistor Q ₂ rises as V _o increases. Since the base potential V ₁ of the transistor Q ₂ is driven by the emitter follower transistor Q _1, it becomes V _o −V _BE (Q ₁ ). The base-emitter voltage of the transistor Q ₂ is V _BE (Q ₂ ) = V _o −V _BE (Q ₁ ) −V _o = −V _BE (Q ₁ ) ... (2) The reverse voltage between the emitter and emitter does not exceed about 0.7 V (Fig. 2B). When the voltage V _o <0, as V _o becomes smaller, emitter capacitor potential of the transistor Q ₁ is lowered, Q ₁ is turned off upon reaching a V _o = V _CL (B in FIG. 2). When V _o further decreases, Q ₂ starts to conduct. Of base Q ₂ - Since the ground potential is leaning against the coercive almost V _CL, the emitter potential of the V _o ie Q ₂ is _{V o = V CL -V BE (} Q 2) ... (3) does not decrease than. That is, the clamp voltage is approximately V _CL −0.7V (C in FIG. 2).

According to the output amplitude limiting circuit having such a configuration, the first transistor (Q₁, Q ₃ ) Emitter-follower output of the second clamp transistor (Q₂, Q_Four) Of the second transistor (Q₂, Q_FourBy making the base potential of) follow the output of the amplification stage, the clamping transistor (Q₂, Q_Four) The reverse voltage between the base emitters is V_BESince it does not exceed (about 0.7 V), high-speed transistors with a small base-emitter reverse breakdown voltage can output with a large amplitude.

[0011]

[Effect of the device]

 As described above, according to the present invention, an output amplitude limiting circuit capable of large-amplitude output can be realized with a simple configuration by using a clamp transistor having a low reverse breakdown voltage between the base and the emitter. ..

[Brief description of drawings]

FIG. 1 is a configuration circuit diagram showing an embodiment of an output amplitude limiting circuit according to the present invention.

FIG. 2 is a characteristic curve diagram showing the operation of the circuit of FIG.

FIG. 3 is a configuration circuit diagram showing a conventional output amplitude limiting circuit.

[Explanation of symbols]

2 amplification stage 3 output amplitude limiting circuit N output terminal V _CC , V _EE voltage source Q ₁ , Q ₃ first transistor V _CH , V _CL clamp voltage R ₁ , R ₂ resistance Q ₂ , Q ₄ second transistor

Claims (1)

[Scope of utility model registration request] 1. A first transistor having a base terminal connected to an output terminal of an amplification stage and a collector terminal connected to a voltage source, and one end of which is connected to an emitter terminal of the first transistor and the other end of which is clamped. A resistor connected to the voltage; and a second transistor having a base terminal connected to the emitter terminal of the first transistor, a collector terminal connected to the voltage source, and an emitter terminal connected to the output terminal of the amplification stage. An output amplitude limiting circuit characterized by being provided.