JP2914145B2 - Pulse output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse output circuit for amplifying a pulse signal having a predetermined amplitude to a power supply voltage level and outputting the amplified signal.

[0002]

2. Description of the Related Art A conventional pulse output circuit will be described with reference to FIGS. FIG. 3 is a connection diagram showing a configuration of a conventional pulse output circuit. In FIG. 3, the pulse output circuit 1 is
Input terminal 2, output terminal 3, power supply terminal 4, and ground terminal 5
Thus, a pulse signal having a predetermined amplitude is input to the input terminal 2. The low level of this pulse signal is about 0 [V], and the high level is a positive voltage sufficiently lower than the power supply voltage VCC. Input terminal 2
Is divided by the resistors R1 and R2 and input to the base terminal of the transistor Q1.
The collector terminal of this NPN transistor Q1 is connected to a resistor R
The power supply terminal 4 is connected to the power supply terminal 3 via the terminal 3 and the emitter terminal is grounded. That is, NPN transistor Q1 forms a common emitter circuit. Similarly, the PNP transistor Q2 also forms a grounded-emitter circuit, the base terminal of which is connected to the collector terminal of the NPN transistor Q1, and the collector terminal of which is connected to the output terminal.

FIG. 4 is a signal waveform diagram showing each terminal voltage of the pulse output circuit 1. The operation of the conventional pulse output circuit shown in FIG. 3 will be described with reference to FIG. The pulse signal input to the input terminal 2 is divided by the resistors R1 and R2 and input to the base terminal of the NPN transistor Q1.
As a result, the base voltage of the NPN transistor Q1 becomes
The voltage level changes between 0 [V] and a predetermined voltage following the change in the signal level of the pulse signal (see FIG. 4).

When the base voltage of NPN transistor Q1 is 0
When the voltage becomes [V], that is, the low level, the NPN transistor Q1 shifts to the cutoff region, that is, is turned off. Conversely, when the base voltage exceeds the cutoff voltage determined by the base-collector current conversion characteristic of the NPN transistor Q1. , NPN transistor Q1 shifts to the saturation region via the operation region and turns on.

When the NPN transistor Q1 is off, no collector current flows through the resistor R3.
The base voltage of transistor Q2 is substantially equal to power supply voltage VCC. Therefore, PNP transistor Q2 is turned off, the collector current does not flow, and the terminal voltage of output terminal 3 attains the ground voltage level of 0 [V].

On the other hand, when the NPN transistor Q1 is turned on, a collector current flows through the resistor R3.
The base voltage of P transistor Q2 drops from power supply voltage VCC to a predetermined voltage. Therefore, the PNP transistor Q
2 is also turned on, the collector current flows and the output terminal 3
Is almost equal to the power supply voltage VCC.

As described above, even when the signal amplitude of the pulse signal input to the input terminal 2 is sufficiently small as shown in FIG. 4, the output terminal 3 outputs a pulse signal having an amplitude substantially close to the power supply voltage value. You.

[0008]

In the conventional pulse output circuit shown in FIG. 3, when the pulse signal input to the input terminal 2 goes low, the transistors Q1 and Q
2 are both turned off, and a voltage close to the power supply voltage Vcc is applied between each emitter and collector of the transistors Q1 and Q2. Therefore, if the voltage value of power supply voltage VCC is increased to increase the signal amplitude of the pulse signal output from output terminal 3, the emitter-collector voltage of transistors Q1 and Q2 increases accordingly. Therefore, if the voltage value of the power supply voltage is too large, the breakdown voltage of the transistor may be exceeded and the transistor may be broken. That is, in the conventional pulse output circuit shown in FIG. 3, since the voltage value of the power supply voltage VCC cannot be higher than the withstand voltage value of the transistor, there is a problem that the amplitude of the signal output from the pulse output circuit cannot be increased after all.

An object of the present invention is to set a voltage applied between an emitter and a collector of a transistor to a predetermined voltage level lower than a power supply voltage level when the transistor is in an off state, so that a power supply voltage higher than a withstand voltage value of the transistor is set. To provide a pulse output circuit capable of applying the pulse output.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to FIG. 1 showing an embodiment. The present invention inverts an input signal which repeats a high level state and a low level state whose voltage value is smaller than a power supply voltage. A first NPN transistor Q1 having a common-emitter circuit configuration for amplifying the first NPN transistor Q1;
A first PNP transistor Q2 that inverts and amplifies the collector terminal voltage of transistor Q1, is connected between the collector terminal of first PNP transistor Q2 and the ground terminal, and outputs a pulse signal obtained by inverting and amplifying an input signal. This is applied to a pulse output circuit having an output terminal 3.
(A) A second NPN transistor Q is connected between the collector terminal of the first NPN transistor Q1 and the power supply terminal 4.
(B) first and second resistors R5 and R6 for setting the power supply voltage by dividing the power supply voltage are connected to the base terminal of the second NPN transistor Q3, and (c) the second NPN transistor The base terminal of the first PNP transistor Q2 is connected to the collector terminal of Q3, and (d) the second PNP transistor Q5 is inserted between the collector terminal of the first PNP transistor Q2 and the output terminal 3; ) This second PN
When the first PNP transistor Q2 is on, the second terminal is located between the base terminal of the P transistor Q5 and the power supply terminal 3.
The voltage of the base terminal of the PNP transistor Q5 is set lower than the voltage of the emitter terminal thereof, and when the first PNP transistor Q2 is off, the second PNP transistor Q5
Voltage setting means Q4, Q6, R8, and R9 for setting the voltage of the base terminal of the first PNP transistor to a voltage lower than the power supply voltage, and when the input signal is low and the first NPN transistor Q1 is off, the first PNP transistor Q2 is turned off, and the voltages of the collector terminal of the first NPN transistor Q1 and the collector terminal of the first PNP transistor Q2 are set to voltages lower than the power supply voltage, so that the first NPN transistor Q1 and the first PNP transistor When the input signal is at a high level and the first NPN transistor Q1 is turned on, the first PNP transistor Q2 is turned on, and the voltage at the collector terminal of the collector terminal is changed to the power supply voltage. By configuring the power supply voltage level from a voltage lower than the voltage to approximately the power supply voltage level, It is achieved.

[0011]

[0012]

When the base terminal voltage of the first NPN transistor Q1 becomes low level, the first NPN transistor Q1 is turned off, the first PNP transistor Q2 is turned off, and the collector of the first NPN transistor Q1 is turned off. Set the voltage lower than the power supply voltage. The voltage setting means Q4, Q6, R8, R9 set the collector voltage of the first PNP transistor Q2 to a voltage lower than the power supply voltage. As a result, the emitter-collector voltage of the first NPN transistor Q1 and the emitter-collector voltage of the first PNP transistor Q2 are set to a level lower than the power supply voltage, and the output level from the output terminal is substantially grounded. Voltage level. On the other hand, when the base terminal voltage of the first NPN transistor Q1 becomes high level,
This first NPN transistor Q1 is turned on and the first P
While turning on the NP transistor Q2, the voltage setting means Q4, Q6, R8, and R9 set the voltage at the collector terminal of the first PNP transistor Q2 from a voltage lower than the power supply voltage to substantially the power supply voltage level. As a result, the output level from the output terminal becomes approximately the power supply voltage level.

[0013]

In the means and means for solving the above problems which explain the constitution of the present invention, the drawings of the embodiments are used for easy understanding of the present invention. However, the present invention is not limited to this.

[0015]

1 and 2, an embodiment of the present invention will be described. FIG. 1 is a circuit diagram of one embodiment of a pulse output circuit according to the present invention. Components common to those in the conventional pulse output circuit shown in FIG. Will be described. In FIG. 1, reference numeral 11 denotes a collector terminal of an NPN transistor Q1 having a common-emitter circuit configuration and a transistor Q1 having the same common-emitter circuit configuration.
2 is a first voltage setting circuit interposed between the first and second base terminals. The first voltage setting circuit 11 includes an NPN transistor Q3 and resistors R5, R6, and R7.
Resistors R5 and R6 are connected to the base terminal of N transistor Q3.
, A voltage value obtained by dividing the power supply voltage VCC is input.
The collector terminal of the NPN transistor Q3 is a PNP
Connected to the base terminal of transistor Q2,
The emitter terminal of N transistor Q3 is connected to the collector terminal of NPN transistor Q1 via resistor R7.

The first voltage setting circuit 11 operates so that when the NPN transistor Q1 is in the off state, the voltage between the emitter and the collector thereof becomes approximately VCC / 2 [V]. Control is performed so that the base terminal voltage becomes approximately VCC [V].

Reference numeral 12 denotes a second voltage setting circuit interposed between the collector terminal of the PNP transistor Q2 and the output terminal 3. This second voltage setting circuit 12 is a PNP
It comprises transistors Q4, Q5, Q6 and resistors R8, R9. The emitter terminal and base terminal of PNP transistor Q4 are connected to the emitter terminal and base terminal of PNP transistor Q2, respectively, and the emitter terminal and collector terminal of PNP transistor Q4. Is the resistance R
8 are connected. On the other hand, the PNP transistor Q5
Are connected to the collector terminal and output terminal 3 of PNP transistor Q2, respectively. A PN is connected between the collector terminal of the PNP transistor Q4 and the base terminal of the PNP transistor Q5.
P transistor Q6 is interposed. The base terminal and the collector terminal of the PNP transistor Q6 are connected to each other, whereby the PNP transistor Q6 functions as a diode having its emitter terminal as an anode and its base terminal as a cathode.

When the PNP transistor Q2 is off, the second voltage setting circuit 12 sets the emitter-collector voltage of the PNP transistor Q2 to about VCC / 2 [V].
, And at this time, the voltage of the output terminal 3 is controlled to be 0 [V] which is the ground level. On the other hand, P
When the NP transistor Q2 is on, the output terminal 3
Is controlled to be about VCC.

FIG. 2 is a signal waveform diagram showing the terminal voltages of the pulse output circuit shown in FIG. 1. The operation of this embodiment will be described with reference to FIG. The pulse signal input to the input terminal 2 is divided by the resistors R1 and R2 and input to the base terminal of the NPN transistor Q1 (see FIG. 2A). When the pulse signal goes high, the NPN transistor Q1 turns on and its collector terminal voltage decreases, and when it goes low it turns off and its collector terminal voltage rises. That is, the NPN transistor Q1 inverts and amplifies the pulse signal.

The voltage V1 divided by the resistors R5 and R6 is input to the base terminal of the NPN transistor Q3 in the first voltage setting circuit 11, and its value is expressed by a pulse signal as shown in the equation (1). Are constant regardless of the signal level (see FIGS. 2A and 2B).

(Equation 1)

When the NPN transistor Q1 is off, no current flows through the resistor R7, so that the NPN transistor Q3 is also off and the NPN transistor Q1 is turned off.
3, the base terminal voltage and the emitter terminal voltage are substantially equal, and the collector terminal voltage of the NPN transistor Q3 is substantially equal to the power supply voltage VCC. Thus, for example, when the values of resistors R5 and R6 are equal, the voltage between the emitter and the collector of NPN transistor Q3 becomes approximately VCC / 2.
[V], and similarly, the voltage between the emitter and the collector of the NPN transistor Q1 also becomes about VCC / 2 [V].

As described above, when the NPN transistor Q1 is off, only a voltage of about VCC / 2 [V] is applied between the emitter and the collector of the NPN transistor Q1, so that the conventional pulse output circuit shown in FIG. In comparison, the magnitude of the power supply voltage VCC can be approximately doubled.

On the other hand, when the NPN transistor Q1 is off, the collector terminal of the NPN transistor Q3, that is, the base terminal of the PNP transistor Q2 is at about VCC [V] as described above (see FIG. 2A). PN
P transistor Q2 is also turned off. Similarly, the base terminal of the PNP transistor Q4 in the second voltage setting circuit 12 also has a voltage of about VCC [V].
4 is also turned off. Also, since the PNP transistor Q6 is diode-connected, the PNP transistor Q6
5 has a voltage value divided by the resistors R8 and R9 and the base-emitter voltage VBE6 of the PNP transistor Q6 as shown in the equation (2) (see FIG. 2B).

(Equation 2)

When the PNP transistor Q2 is off, no current flows through the emitter terminal of the PNP transistor Q5, so that the PNP transistor Q5 is also off. Therefore, the collector terminal voltage of PNP transistor Q5 becomes 0 [V], which is the ground voltage level, and its emitter terminal voltage becomes substantially equal to the base terminal voltage shown in equation (2). Thus, for example, if the values of the resistors R8 and R9 in the equation (2) are made equal, the emitter-collector voltage when the PNP transistor Q2 is off is
It is about VCC / 2.

As described above, the second voltage setting circuit 12
When the NPN transistor Q1 is turned off, that is, the PNP transistor Q2 is turned off, control is performed so that a voltage lower than the power supply voltage VCC is applied between the emitter and the collector of the PNP transistor Q2.

On the other hand, when the NPN transistor Q1 is turned on, a current flows from its collector terminal to the emitter terminal and the voltage between the emitter and the collector drops, so that the emitter of the NPN transistor Q3 in the first setting circuit 11 The voltage level of the terminal decreases, and the NPN transistor Q3 also shifts to the saturation region and turns on. As a result, the emitter-collector voltage of the NPN transistor Q3 decreases, and the collector terminal voltage of the NPN transistor Q3, that is, the base terminal voltage of the PNP transistor Q2 decreases (see FIG. 2A). Therefore, both PNP transistor Q2 and PNP transistor Q4 shift to the saturation region and are turned on. When the PNP transistor Q4 is turned on, the emitter-collector voltage drops, and the base terminal voltage V2 of the diode-connected PNP transistor Q6 has the voltage value shown in the equation (3) (see FIG. 2B). .

(Equation 3)

Further, when the PNP transistor Q2 is turned on, the emitter terminal voltage of the PNP transistor Q5 rises, whereby the PNP transistor Q5
Shifts to the saturation region and turns on. At this time, as described above, the base terminal voltage of the PNP transistor Q6, that is, the base terminal voltage of the PNP transistor Q5 is
Since the value is close to the power supply voltage VCC as shown in the equation (3), the output terminal voltage connected to the collector terminal of the PNP transistor Q5 rises to about VCC (FIG. 2).
(A)).

As described above, the second voltage setting circuit 12
When the pulse signal input to the input terminal 2 goes high, the PNP transistor Q5 is turned on, and its base voltage is raised to near the power supply voltage level, so that the voltage value at the output terminal 3 is almost equal to the power supply voltage. Change to VCC.

In the embodiment described above, a first power supply setting circuit 11 and a second power supply setting circuit 12 are newly provided in the conventional pulse output circuit shown in FIG.
When the pulse signal input to the
Since the emitter-collector voltage of each of the transistor Q1 and the PNP transistor Q2 is set to a voltage lower than the power supply voltage VCC, the magnitude of the power supply voltage VCC input to the power supply terminal 4 may be equal to or larger than the withstand voltage of the transistor. it can. Further, when the pulse signal input to the input terminal 2 becomes high level, the voltage of the output terminal 3 is almost equal to the power supply voltage. Therefore, the amplification factor (gain amount) of the pulse signal input to the input terminal 2 is increased. can do.
Further, in the above embodiment, since the pulse output circuit is constituted only by the transistor and the resistor, the entire circuit can be easily formed into an integrated circuit.

In the above embodiment, the circuit configuration of the first voltage setting circuit 11 and the second voltage setting circuit 12 is not limited to the embodiment. For example, although the transistor Q6 is used as a diode, a normal diode may be used.

In the embodiment configured as described above, N
The PN transistor Q1 becomes the first NPN transistor,
PNP transistor Q2 is the first PNP transistor, NPN transistor Q3 is the second NPN transistor, resistor R5 is the first resistor, and resistor R6 is the second.
, The PNP transistor Q5 corresponds to a second PNP transistor, and the PNP transistors Q4 and Q6 and the resistors R8 and R9 correspond to voltage setting means.

[0032]

As described above in detail, according to the present invention, when the base terminal voltage of the first NPN transistor goes low, the first NPN transistor and the first PNP transistor are turned off, The first N
Since the voltage at the collector terminal of the PN transistor and the voltage at the collector terminal of the first PNP transistor are set lower than the power supply voltage, the voltage between the emitter and collector terminals of both transistors can be made lower than the power supply voltage. As a result, a higher power supply voltage can be applied to the power supply terminal. Also, when the base terminal voltage of the first NPN transistor goes to a high level, the first PNP
Since the voltage at the collector terminal of the transistor is set to approximately the power supply voltage level, when a higher power supply voltage is applied, a higher output signal level is output from the output terminal to the level of the pulse signal input to the input terminal. Obtainable.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of a pulse output circuit according to the present invention.

FIG. 2 is a waveform chart showing waveforms at various parts in FIG.

FIG. 3 is a circuit diagram of a conventional pulse output circuit.

FIG. 4 is a waveform chart showing waveforms at various parts in FIG. 3;

[Explanation of symbols]

 1 pulse output circuit 2 input terminal 3 output terminal 4 power supply terminal Q1 to Q6 Transistor R1 to R9 Resistance

Claims (1)

(57) [Claims] 1. A first NPN transistor having a common emitter circuit configuration for inverting and amplifying an input signal which repeats a high level state and a low level state having a voltage value smaller than a power supply voltage, and a collector terminal voltage of the first NPN transistor A first PNP transistor for inverting and amplifying the input signal, and an output terminal connected between the collector terminal and the ground terminal of the first PNP transistor for outputting a pulse signal obtained by inverting and amplifying the input signal. In the output circuit: (a) a collector terminal of the first NPN transistor
A second NPN transistor between the source terminal and
(b) A power supply is connected to the base terminal of the second NPN transistor.
Connect the first and second resistors to set the voltage by dividing
(C) the collector terminal of the second NPN transistor
To the base terminal of the first PNP transistor
(D) a collector terminal of the first PNP transistor
Via a second PNP transistor between the output terminal
(E) the base terminal of this second PNP transistor
Between the power supply terminal and the first PNP transistor
When on, the base end of the second PNP transistor
The voltage of the child is set lower than the voltage of the emitter terminal,
When the first PNP transistor is off, the second PNP transistor is turned off.
The voltage at the base terminal of the NP transistor is lower than the power supply voltage
Voltage setting means for setting the voltage to a low level , and when the input signal is at a low level, the first NPN transistor
Turns off the first PNP transistor when is off
And the collector of the first NPN transistor.
Terminal and the collector of the first PNP transistor
The voltage of the terminal is set to a voltage lower than the power supply voltage and the first N
Emitter collector of PN and first PNP transistor
The first NPN transistor when the input signal is at a high level,
Turns on the first PNP transistor when is turned on
And the voltage at its collector terminal is
A pulse output circuit for setting a lower voltage to a power supply voltage level .