JPH10341119A - Differential amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a simple circuit to employ each amplifier transistor(TR) with a low breakdown voltage by devising it that a small voltage is applied to each amplifier TR. SOLUTION: Input terminals 1 and 2 are respectively connected to the base of amplifiers TR T1 and T2. Both emitters are connected together. A control TR T3 and a load resistor R1 are connected in series with a collector of the amplifier TR T1 in this order, the emitter of the control TR T3 is connected to the collector of the amplifier TR T3 and the collector of the TR T3 is connected to the load resistor R1 respectively, and an output terminal 3 is connected to a connecting point between the collector of the control TR T3 and the load resistor R1. A load resistor R2 is connected to the collector of the other amplifier TR T2 and the base of the control TR T3 is connected to the connecting point between the collector of the TR T2 and the load resistor R2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a differential amplifier circuit.

[0002]

2. Description of the Related Art A differential amplifier circuit shown in FIGS. 5 to 7 is used as an input circuit of a multistage amplifier circuit. In the differential amplifier circuit (hereinafter referred to as Conventional Example 1) shown in FIG. 5, NPN bipolar transistors having the same characteristics are used as the amplification transistors (differential transistors) T5 and T6, and an input terminal is provided at each base. 7, 8 are connected, and both emitters are connected to each other.
, A negative voltage -Vee is applied. The collectors of the two amplifying transistors T5 and T6 have load resistors R5 and R5.
R6 is connected to one end, and the load resistance R
5, and the other end of R6 are connected, and a positive voltage + Vcc is applied to these other ends. Output terminals 10 and 11 are connected to connection points between the collectors of the amplification transistors T5 and T6 and the load resistors R5 and R6, respectively.

The differential amplifier circuit shown in FIG. 6 (hereinafter referred to as Conventional Example 2) further includes a pair of additional transistors T7 and T8 and a constant voltage source 12 in addition to the circuit shown in Conventional Example 1. Thus, it is a cascode amplifier circuit. Specifically, each of the additional transistors T7 and T8 is an NPN bipolar transistor, and
5, T6 and each load resistor R5, R6, each emitter is connected to the collector of each amplification transistor T5, T6,
The collector is each load resistance R5, R6 and each output terminal 10, 1.
1, the bases of the additional transistors T7 and T8 are connected to each other, and the constant voltage source 12 is connected to this.

Further, a differential amplifier circuit shown in FIG. 7 (hereinafter referred to as Conventional Example 3) is obtained by removing one output terminal 11 from the circuit shown in Conventional Example 1.

[0005]

In the case of the conventional example 1, especially when the next stage amplifier circuit is directly connected to the differential amplifier circuit of the conventional example 1 and the output voltage is increased, the load resistors R5 and R6 are required. In this case, the voltage drop cannot be increased, and a high DC voltage is inevitably applied to each of the amplifying transistors T5 and T6. Therefore, it is necessary to use a transistor with a high breakdown voltage as the amplifying transistors T5 and T6. In particular, the field effect transistors (FE) are used as the amplification transistors T5 and T6.
When T) is used, not only are there few types of FETs with a high breakdown voltage, but also when the applied voltage is high, the gate leakage current increases, leading to a problem of deteriorating the performance of the differential amplifier circuit. . Further, in the conventional example 1, each amplifying transistor T
5, since the collector potential fluctuates due to the amplifying action of T6, a decrease in gain in a high frequency range due to the Miller effect has also been a problem.

On the other hand, in the conventional example 2, since the applied voltage to the amplifying transistors T5 and T6 is clamped at a constant voltage, the applied voltage can be suppressed low and the collectors of the amplifying transistors T5 and T6 can be reduced. Since there is no change in the potential, a decrease in gain in a high frequency range due to the Miller effect does not pose a problem. However, in the second conventional example, it is necessary to provide the pair of additional transistors T7 and T8 and the constant voltage source 12, so that the number of components is greatly increased, and the differential amplifier circuit is complicated.

Further, the third conventional example has the same problem as the first conventional example.

[0008] An object of the present invention is to provide a differential amplifier circuit that can solve the above problem.

[0009]

In order to achieve the above object, the present invention is characterized in that it has a control electrode to which an input terminal is connected, and first and second main electrodes. It has a pair of amplifying transistors connected to a main electrode, and a pair of load resistors connected to a second main electrode of each amplifying transistor, and the output terminal is connected only to a connection point between the amplifying transistor on one side and the load resistor. In the differential amplifier circuit
A control transistor is interposed between the amplifying transistor on one side and the load resistor. B. a control electrode connected to a connection point between the amplifying transistor on the other side and the load resistor; C. a first main electrode connected to the second main electrode of the amplification transistor on one side; It has a second main electrode connected to a load resistor on one side and an output terminal. Note that the control electrode of the control transistor may be grounded via a capacitor. Also, a capacitor may be interposed between the control electrode of the control transistor and the driving voltage source of the differential amplifier circuit.

As the transistors, various bipolar transistors and field effect transistors (FETs) are used. A control electrode is a base or a gate, a first main electrode is an emitter or a source, and a second main electrode is a It is a collector or a drain. Note that a bipolar transistor and a field-effect transistor may be used only for the amplification transistor, and only a bipolar transistor may be used for the control transistor.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the first embodiment of the present invention will be described.
An example will be described with reference to the drawing of FIG. 1. FIG. 1 shows a differential amplifier circuit, which is used, for example, as an input circuit of a multi-stage amplifier circuit. In this circuit, each of the amplifying transistors (differential transistors) T1 and T2 has N
Using a PN type bipolar transistor, input terminals 1 and 2 are connected to each base, and both emitters are connected.

A control transistor (clamping transistor) T3 and a load resistor R1 are connected in series to the collector of the amplification transistor T1 on one side (output side) in the above order. As the control transistor T3, an NPN type bipolar transistor having the same conductivity type as the amplification transistors T1 and T2 is used, the emitter of which is the collector of the amplification transistor T1, and the collector of which is a load resistance R.
1 and the output terminal 3 is connected to the node between the collector of the control transistor T3 and the load resistor R1.
Are connected, thereby forming an output-side circuit. In order to increase the output voltage from the output terminal 3,
The resistance value of the load resistor R1 is set small.

The other (non-output) amplifying transistor T2
Is connected to a load resistor R2 to form a non-output side circuit, and a connection point between the collector and the load resistor R2 is connected to a base of a control transistor T3. In a state where an input signal is not input to the input terminals 1 and 2 (a state where an input signal is input), if a current flowing through the non-output side circuit is I,
Collector potential Vc of non-output side amplification transistor T2 =
The resistance value of the non-output-side load resistor R2 is set to be large so that Vcc-R2 · I becomes an appropriate small value.

A DC voltage source (DC power supply) for driving the differential amplifier circuit is connected to the differential amplifier circuit. Specifically, a negative voltage -Vee is applied to the emitters of the amplifying transistors T1 and T2 via the constant current source 5 (a negative voltage source and a negative power supply are connected). Voltage + Vcc
Is applied (a positive voltage source and a positive power supply are connected).

According to the first example, when an input signal is input to each of the input terminals 1 and 2, the input signal is amplified in accordance with the potential difference between the two input signals, and the amplified input signal is
It is output from the output terminal 3 as an output signal. Note that the DC / AC operation characteristics of the differential amplifier circuit viewed from the output side are the same as those of the conventional example 3 shown in FIG. 7, and the control transistor T3 does not affect the amplification operation.

By the way, in the non-output side circuit, the load resistance 2
Of the amplifying transistor T2
The collector potential Vc of the amplifying transistor T2
Voltage to be applied can be reduced.

In the output side circuit, the amplification transistor T
1 is clamped by the control transistor T3, and its potential is calculated from the collector potential Vc of the non-output side amplification transistor T1 by the control transistor T3.
3 minus the base-emitter voltage (eg, about 0.6 V). In this case, the collector potential Vc of the non-output side amplification transistor T2 becomes
Since it is low, the collector potential of the output-side amplification transistor T1 can be lowered, and the voltage applied to the output-side amplification transistor T1 can be lowered.

As described above, in the first example, the voltage applied to each of the amplifying transistors T1 and T2 can be reduced, and it is not necessary to use a transistor having a high breakdown voltage as each of the amplifying transistors T1 and T2. A transistor with a withstand voltage can be used, and as compared with the differential amplifier circuits of the conventional examples 1 and 3, only one control transistor T3 may be added, so that a simple circuit can be obtained.

FIG. 2 shows a second embodiment of the present invention, in which N-channel type junction field effect transistors (JFETs) are used as the amplification transistors T1 and T2. The gate of the
The source and the drain correspond to the base, the emitter, and the collector of the amplification transistors T1 and T2 of the first example, respectively.

According to the second example, similarly to the first example, the voltage applied to each of the amplifying transistors T1 and T2 can be reduced, a transistor with a low breakdown voltage can be used, and the gate leakage current can be reduced. It is possible to prevent the performance of the differential amplifier circuit from deteriorating due to the gate leakage current.

FIG. 3 shows a third embodiment of the present invention. In the configuration of the first embodiment, the base of the control transistor T3 is grounded via a capacitor C. still,
The time constant R2 · C is given by:
It is large enough.

According to the third example, the time constant R2 · C is
Since the frequency is sufficiently high with respect to the frequency of the input / output signal, the collector potential of each of the amplifying transistors T1 and T2 can be set to a constant voltage. Can be considered. Therefore, each amplifying transistor T
There is no change in the collector potentials of T1 and T2, and a decrease in gain in a high frequency range due to the Miller effect can be prevented. Also, the configuration of the differential amplifier circuit is simple because only one capacitor C is added to the configuration of the first example.

FIG. 4 shows a fourth embodiment of the present invention. In the configuration of the first embodiment, a capacitor C is interposed between the base of the control transistor T3 and the positive power supply + Vcc.

According to the fourth example, the amplification characteristic is the same as that of the third example, and similarly, it is possible to prevent a decrease in gain in a high frequency range due to the Miller effect. Further, when the power is turned on, the current to the output-side amplification transistor T1 is cut off, so that it is possible to prevent a problem that the entire current flows to the non-output-side amplification transistor T2 and the output-side amplification transistor T1 does not rise.

In the above-described embodiment, only the amplifying transistor of the first example is replaced with an FET. However, the amplifying transistor of the third and fourth examples can be replaced with an FET. .

[0026]

As described in detail above, according to the present invention,
Without affecting the amplification operation, the voltage applied to each amplification transistor can be reduced with a simple circuit,
As each amplifying transistor, a transistor having a low withstand voltage can be used. When the amplifying transistor is a field effect transistor (FET), the gate leakage current can be further reduced, and the performance of the differential amplifier circuit can be prevented from deteriorating due to the gate leakage current.

According to the second aspect, a decrease in gain in a high frequency range due to the Miller effect can be prevented. According to the third aspect, it is possible to prevent a decrease in gain in a high frequency range due to the Miller effect. Further, when the power is turned on, the current to the output-side amplifying transistor is cut off, and the problem that the entire current flows to the non-output-side amplifying transistor and the output-side amplifying transistor does not start can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first example of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second example of the embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third example of the embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth example of the embodiment of the present invention.

FIG. 5 is a circuit diagram showing a first conventional example.

FIG. 6 is a circuit diagram showing a second conventional example.

FIG. 7 is a circuit diagram showing a third conventional example.

[Explanation of symbols]

 1, 2 input terminal 3 output terminal 5 constant current source C capacitor R1, R2 load resistance T1, T2 amplifying transistor T3 control transistor

Claims (3)

[Claims] A control electrode to which an input terminal is connected;
A pair of amplifying transistors having first and second main electrodes and both first main electrodes connected thereto, and a pair of load resistors connected to the second main electrode of each amplifying transistor; In a differential amplifier circuit in which an output terminal is connected only to a connection point between a transistor and a load resistor, a control transistor is interposed between the amplifying transistor on one side and the load resistor, and the control transistor includes: B. a control electrode connected to a connection point between the amplifying transistor on the other side and the load resistor; B. a first main electrode connected to a second main electrode of the amplification transistor on one side; A differential amplifier circuit comprising a load resistor on one side and a second main electrode connected to an output terminal. 2. The differential amplifier circuit according to claim 1, wherein the control electrode of the control transistor is grounded via a capacitor. 3. The differential amplifier circuit according to claim 1, wherein a capacitor is interposed between a control electrode of the control transistor and a driving voltage source of the differential amplifier circuit.