JPH0554072B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a peak voltage detection circuit, and particularly to a peak voltage detection circuit for detecting the peak voltage value of an electrical signal, the entire circuit of which can be integrated into an integrated circuit. It is related to.

[Technical background of the invention]

A conventional peak voltage detection circuit has a circuit configuration as shown in FIG. 1, for example.

That is, the emitter 1 ₂ of the first transistor Q ₁ whose base 1 ₁ is connected to the input terminal 10 and the emitter 2 ₂ of the second transistor Q ₂ are connected, and a current source is connected between these emitters 1 ₂ , 2 ₂ and the ground. I is connected. Further, a sixth transistor _{Q6 ,} a fifth transistor _Q5 , a _third resistor R3, and a fourth resistor R are connected to the collector ₁₃ of the first transistor _Q1 and the collector ₂₃ of the second transistor Q2. A current mirror circuit consisting of ₄ is connected. In addition, the collector _{4 3 of} the second transistor Q ₂ is connected to the power supply 1
The base ₄₁ of the fourth transistor _Q4 connected to the second transistor Q2 is connected to the clamp circuit 6, and the emitter ₄₂ of the fourth transistor _Q4 is connected to the load resistor _R5 , the base ₂₁ of the second transistor _Q2 , A peak hold capacitor C is connected, and this point is connected to the output terminal 11.

The operation of this circuit is explained as follows. That is, when the signal voltage V _i applied to the input terminal 10 becomes larger than the voltage V _p of the output terminal 11, the first
transistor Q ₁ is on, the second transistor
Q ₂ is turned off. and the first transistor Q ₁
When a current i flows through the fifth transistor Q ₅ ,
The sixth transistor Q ₆ , the third resistor R ₃ and the fourth
A current of approximately i also flows through the fifth transistor _Q5 due to the current mirror circuit consisting of the resistor _R4 . This current turns on the fourth transistor Q ₄ and the voltage V _p at the output terminal 11 increases. In this way, when V _p becomes larger than V _i , the first transistor Q ₁ turns off, the second transistor Q ₂ turns on, and the second transistor Q 1 turns off.
The voltage at the collector 2 ₃ of Q ₂ decreases and the fourth transistor Q ₄ is turned off, so that V _p stops rising.
In this way, the peak value of the voltage applied to the input terminal 10 is held at the output terminal 11. When the input voltage V _i decreases, the second transistor Q ₂ turns on, and since the voltage at the collector 2 ₃ of the second transistor Q ₂ decreases, the fourth transistor Q ₄ turns off, and the output voltage becomes approximately C× It goes down with a time constant of R ₅ .

[Problems with background technology]

However, in this circuit, if you want to set the time constant to a relatively long value, R ₅ or C
However, in integrated circuits, the value of C cannot be made very large. Furthermore, even if the value of the resistor can be increased, the area occupied by the resistor will increase, resulting in an increase in chip size.

Furthermore, if the input impedance of the circuit connected to the output terminal 11 is low, there is no point in increasing _R5 .

As described above, integrated circuits have had the problem that it is extremely difficult to create a peak voltage detection circuit with a long time constant using the circuit shown in FIG.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned conventional problems, and it is an object of the present invention to provide a peak voltage detection circuit that can be formed into a small integrated circuit and that can perform peak hold on higher-speed signals.

[Summary of the invention]

That is, a first transistor whose base is an input terminal, and a second transistor having the same polarity as the first transistor.
a current source or a resistor connected to both emitters of the first transistor and the second transistor, a first load connected to the collector of the second transistor, and a power source connected to the load; The second transistor has a collector connected to the power supply, a second transistor having a base connected to the emitter of the first transistor, and a collector of which is grounded. 5 transistors,
2 connected to the emitter of the fifth transistor
a fourth series diode, the base of which is connected to the other end of the diode, the collector of which is connected to the power source, and the emitter of which is connected to the collector of the second transistor;
a capacitor having one end connected to the emitter of the third transistor and the other end grounded; a fourth transistor having a base connected to the capacitor and a collector connected to the power source;
A peak voltage detection circuit comprising: a second load connected to the emitter of the fourth transistor; and an output terminal configured by the emitter of the fourth transistor connected to the base of the second transistor.

[Embodiments of the invention]

Next, one embodiment of the present invention will be explained with reference to FIG. In the figure, the same reference numerals as in FIG. 1 are given the same reference numerals. However, the numbers for the base, emitter, and collector of the transistor are omitted.

That is, the first terminal whose base is connected to the input terminal 10
The emitter of the transistor Q ₁ is connected to the emitter of the second transistor Q ₂ and the collector of the ninth transistor Q ₉ which serves as a current source. A fifth transistor Q ₅ is connected to the collector of the first transistor Q ₁ and the collector of the second transistor Q ₂ .
A current mirror circuit consisting of a sixth transistor _Q6 , a third resistor _R3 and a fourth resistor _R4 is connected. The collector of the second transistor Q ₂ has
The base of a third transistor Q ₃ whose collector is connected to the power supply 12 is connected to the emitter of a twelfth transistor Q ₁₂ for clamping. A second resistor is connected to the emitter of the third transistor _Q3 .
_R2 is connected to the other end of this second resistor _R2 , and the peak hold capacitor C and collector are connected to the power supply 1.
The base of a fourth transistor _Q4 connected to Q2 is connected. The emitter of the fourth transistor Q ₄ is connected to the base of the second transistor Q ₂ and the load resistor R ₅ , and this point is connected to the output terminal 11 . The base of the twelfth transistor Q ₁₂ whose collector is connected to the power supply 12 is connected to two diodes D ₁ and D ₂ connected in series with a ninth resistor R ₉ whose one end is connected to the power supply 12. The other ends of the diodes D ₁ and D ₂ are connected to the emitter of an eleventh transistor Q ₁₁ whose collector is grounded, and the base of this eleventh transistor Q ₁₁ is connected to the emitter of the first transistor Q ₁ . There is. Furthermore, a tenth transistor Q10 whose collector and base are connected to a tenth resistor _R10 whose one end is connected to the power supply ₁₂ has its emitter grounded.
The base of the tenth transistor _Q10 is connected to the base of the ninth transistor _Q9 . In addition, the 9th
Even if a resistor is connected in place of the transistor _Q9 , it functions in exactly the same way.

Next, to explain the operation of this circuit, input terminal 1
When the signal voltage V _i added to 0 becomes larger than the voltage V _p of the output terminal 11, the first transistor Q ₁ is turned on and the second transistor Q ₂ is turned off. And when current i flows through the first transistor _Q1 ,
fifth transistor Q ₅ , sixth transistor Q ₆ ,
Due to the current mirror circuit consisting of the third resistor R ₃ and the fourth resistor R ₄ , a current of approximately i flows through the fifth transistor Q ₅ , and this current causes the third
Transistor _Q3 turns on and capacitor C
is charged up, and the voltage _Vp at the output terminal 11 increases through the fourth transistor _Q4 .
When V _p becomes larger than V _i , the first transistor
Q ₁ is turned off, the second transistor Q ₂ is turned on, the collector voltage of the second transistor Q ₂ decreases, and the third transistor Q ₃ is turned off, so that V _p stops rising. In this way, the peak value of the voltage applied to the input terminal 10 is held at the output terminal 11. When the input voltage V _i decreases, the second
transistor Q ₂ is turned on and the voltage at the collector of this second transistor Q ₂ is reduced, so the third transistor Q ₂ is turned off and the output voltage V _p
decreases approximately with the time constant of h _FE of C × R ₅ × Q ₄ .

At this time, the voltage of the second transistor is approximately V _p +V _BE (0.7V) by the clamp circuit consisting of the 11th transistor Q ₁₁ , the 12th transistor Q ₁₂ diodes D ₁ , D ₂ , and the 9th resistor R ₉ It is clamped to prevent the second transistor _Q2 from becoming saturated.

As described above, according to this embodiment, it is possible to easily create a time constant that is larger than the conventional one by h _FE times that of the fourth transistor Q ₄ .

Note that in this circuit, the second resistor R ₂ is a resistor for suppressing overshoot of the output voltage when the input signal rise time is fast, and when the input signal rise time is slow, the second resistor R ₂ The emitter of the third transistor _Q3 , the base of the fourth transistor _Q4, and the capacitor C may be directly connected without inserting the capacitor C.

Next, a first modification of this embodiment will be explained with reference to FIG. In the drawings, the same reference numerals as those in the embodiment indicate the same parts and will not be particularly described.

That is, the difference between this modification and the embodiment is that the collector of the first transistor _Q1 is directly connected to the power supply 12;
The collector of the second transistor Q ₂ is connected to a fifteenth transistor Q ₁₅ as a simple current source load, and the current source I is connected to the emitters of the first transistor Q ₁ and the second transistor Q ₂ . _E is set to twice the 15th transistor current I _Q15 , and when the input and output voltages are equal, equal currents flow through the first transistor _Q1 and the second transistor _Q2 , suppressing input and output errors. There is.

The circuits in Figures 2 and 3 described above detect the positive peak voltage of the signal, but by replacing the npn transistor in these circuits with a pnp transistor and the pnp transistor with an npn transistor, they detect the negative peak of the signal. It is also possible.

Next, FIG. 4 shows a circuit diagram in which the circuit in FIG. 2 is replaced with a negative peak detection circuit.

The operation of this circuit is that when the input signal V _i falls, the first transistor Q ₁ is turned on, the second transistor is turned off, and the third transistor Q ₃ is turned on.
The capacitor C is charged, the output voltage V _p decreases, and the negative peak of the input voltage V _i is held.

It is also possible to replace the circuit of FIG. 3 with a negative peak detection circuit using a similar idea.

Furthermore, the load resistor R ₅ in the three circuits described above may be replaced with a current source load. However, in this case, the time constant is expressed as h _FE ×C × output voltage/current value of current source load, and the time constant can be made longer by h _FE times.

Furthermore, if it is acceptable even if the input/output accuracy deteriorates to some extent, it is also possible to use a resistor as the load connected to the collector of the second transistor _Q2 .

〔Effect of the invention〕

The peak voltage detection circuit according to the present invention is characterized in that it is possible to hold the peak of a faster signal. That is, during peak hold, the base-emitter voltage of transistor Q3 becomes 0V. Therefore, when a signal is input, Q3 quickly turns on, making it possible to hold the peak of a high-speed signal. Furthermore, since the clamp voltage is taken from the common emitter of the differential transistors, the clamp circuit itself operates at high speed because the clamp voltage also increases as the input voltage increases.

Moreover, in an integrated circuit, it is possible to form a peak voltage detection circuit with a longer time constant than before, and the industrial value is extremely large.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional peak detection circuit, FIG. 2 is a circuit diagram of an embodiment of the peak detection circuit of the present invention, and FIG. 3 is a circuit diagram showing a modification of the embodiment of FIG. 2. 4 are circuit diagrams showing a modification of the embodiment shown in FIG. 2 in which the type of transistor is changed to detect a negative peak. 10...Input terminal, 11...Output terminal, 12...
…power supply.

Claims (1)

[Claims] 1 a first transistor having a base as an input terminal; a second transistor having the same polarity as the first transistor; a current source or a resistor connected to both emitters of the first transistor and the second transistor; a first load connected to the collector of the second transistor; a power source connected to the load; a third transistor having a base connected to the collector of the second transistor and a collector connected to the power source; a fifth transistor having a polarity opposite to that of the first transistor, the base of which is connected to the emitter of the first transistor, and the collector of which is grounded;
2 connected to the emitter of the fifth transistor
a sixth transistor having a base connected to the other end of the diode, a collector connected to the power source, and an emitter connected to the collector of the second transistor;
a capacitor having one end connected to the emitter of the third transistor and the other end grounded; a fourth transistor having a base connected to the capacitor and a collector connected to the power source;
A peak voltage detection circuit comprising: a second load connected to the emitter of the fourth transistor; and an output terminal configured by the emitter of the fourth transistor connected to the base of the second transistor.