JPH0486569A - Peak holding circuit - Google Patents

Abstract

PURPOSE:To achieve a power saving having a simple circuitry with a shorter charging time of a capacitor for holding voltages by supplying an input signal to the voltage holding capacitor via a current mirror circuit. CONSTITUTION:When a level of an input signal Vs is larger than a terminal voltage of a voltage holding capacitor C to hold a peak value of the input signal Vs as peak holding voltage, a current mirror circuit M supplies a current Ic to hold a voltage equivalent to a peak level with the voltage holding capacitor C following the input signal Vs. At this point, as the current mirror circuit M can supply a large charging current Ic, the charging time of the voltage holding capacitor C can be reduced. This allows the building up of a peak holding circuit which can follow the input signal level fast with a small capacity charging power source along with a simple circuitry. It should be noted that a peak holding voltage Vpk held by the capacitor C is outputted via an output circuit 0 having a high input impedance.

Description

[Detailed Description of the Invention] [Summary] Used to obtain a variable slice level to enable reading of recorded data even when the read level decreases due to dropout etc. in a magnetic recording device. Regarding peak hold circuits, in order to follow the amplitude changes of the input signal at high speed, the charging time of the voltage holding capacitor is short, and the purpose of the peak hold circuit is to obtain a peak hold circuit with a simple circuit configuration and low power consumption. a voltage holding capacitor that holds the value;
In a peak hold circuit comprising an output circuit having a high input impedance for outputting the terminal voltage of the capacitor, and a discharge circuit for discharging the capacitor,
The input signal was configured to be supplied to the voltage holding capacitor via a current mirror circuit.

[Industrial application field]

The present invention relates to a peak hold circuit used to obtain a variable slice level to enable reading of recorded data even when a read level decreases due to dropout or the like in a magnetic recording device.

[Conventional technology]

In conventional magnetic tape devices, an automatic gain control circuit (A
GC circuit) is used to reduce the influence, and data demodulation is performed with the slice level constant.

FIG. 4 shows DDNRZI (doub
le density nonreturn-to-z
5 is a block diagram showing the overall configuration of a data demodulation circuit for recording data (change-on-ones), and FIG. 5 is a waveform diagram for explaining its operation. Note that the part of this circuit that handles analog signals has a configuration using a differential circuit, so that it has good noise resistance.

In FIG. 4, the MR head 1 is a read head such as a magnetoresistive read head that detects the perpendicular component of magnetism recorded on a magnetic recording medium such as a magnetic tape, and the read signal read by this read head 1 is sent to a preamplifier. After being amplified by a factor of 2, the signal is sent to a differential equalizer 3, where it is differentiated, and then sent to a variable gain amplifier 4.

The gain of the variable gain amplifier 4 is determined by an equalizer amplifier 5 connected to the output side of the variable gain amplifier 4, which removes unnecessary frequency components, and then an amplitude adjustment section 6 converts it into a gain control signal obtained as a voltage inversely proportional to the amplitude of this signal. controlled accordingly. That is, the variable gain amplifier 4, equalizer amplifier 5, and amplitude adjustment section 6 constitute an automatic gain control circuit, and the output signal level from the amplitude adjustment section 6 is kept constant.

In FIG. 5, (al is the recording data, (b) is the digital signal recorded on the recording medium, (C1 is the magnetization state of the recording track of the recording medium, and (d) is the output of the preamplifier 12. The signal, (e) is the output of the differential equalizer 13, and (f) is the output of the amplitude adjustment section 17, respectively, for one of the balanced transmission lines.

The output of the amplitude adjustment section 6 shown in FIG. 5(f) is connected to a data separator 7A provided for each system of the balanced circuit configuration.
, 7B and the peak hold circuit 8.

The configuration of this data separator is shown only for one 7A, and includes a level discrimination circuit 71, a J- flip-flop 72, a D flip-flop 73, and an exclusive OR circuit (EOR) 74. The level discrimination circuit 71 receives a signal of “1” when there is an input exceeding the positive and negative slice levels as shown in FIG.
”, and when it exceeds the positive slice level, the “
When the voltage exceeds the slice level on the negative side, pulse outputs of "1" level as shown in FIG. 1 (hl) are output as amplifier sense A and amplifier sense B, respectively.

This amplifier sense A signal is generated based on the peak pulse, and the flip-flop 72 is sent to J- according to the lead clock from the clock generator 9 shown in the figure (jl), and the amplifier sense B signal is generated based on this flip-flop. Since the flop 72 is reset in response to this read clock, the output shown in FIG. 5 (kl) is obtained from the Q output terminal of this flip-flop 72, and the signal shown in Since the output of this D flip-flop 73 is supplied to the input terminal of the D flip-flop 73 as shown in the same figure (1
).

Then, the outputs of the flip-flop 72 and the D flip-flop 73 are connected to the J- terminals of the EOR circuit 74.
This EO
From the output terminal of the R circuit 74, the binary output shown in FIG. 5(m) is obtained, and the high level represents "1" and the low level represents "0", Showed DD?JR
This means that the Zl data has been decoded as NRZ data as shown in the figure (nl).

By the way, in this demodulation circuit, as shown in FIG. If the automatic gain control function using the variable gain amplifier described above is unable to follow the spacing loss that occurs when the data is lost, or the dropout that occurs due to dust or uneven coating of the recording material, data demodulation may become impossible.By the way, Since the slice level is normally set to about 40% of the peak level of a normal input signal, if the peak level of the output of the amplitude adjustment section 17 falls below the slice level, data cannot be read.

In order to solve this problem, it was considered that demodulation would be possible even if the level of the input signal decreased by changing the slice level according to the peak level of the human-powered signal. Since the charging period and discharging period of the capacitor to hold the peak value of the signal are the same, if the slice level temporarily decreases, the amplitude of the signal after recovery will increase, leading to misreading of low-level signals. There is a problem with taking it away.

[Problem to be solved by the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a peak hold circuit with a simple circuit configuration and low power consumption, with a short charging time of a voltage holding capacitor, in order to obtain a slice level that follows amplitude changes of an input signal at high speed.

[Means to solve the problem]

A voltage holding capacitor that holds the peak value of the human input signal,
In a peak hold circuit comprising an output circuit having a high input impedance for outputting the terminal voltage of the capacitor, and a discharge circuit for discharging the capacitor,
The input signal was configured to be supplied to the voltage holding capacitor via a current mirror circuit.

[For production]

As shown in the principle diagram in Figure 1, when the level of the input signal Vs is greater than the terminal voltage of the voltage holding capacitor C that holds the peak value of the input signal Vs as a peak hold voltage, the current mirror circuit M follows the input signal. A current 1c for holding a voltage corresponding to the peak level is supplied to the voltage holding capacitor C.

At this time, since the current mirror circuit M can supply a large charging current Ic, the charging time of the voltage holding capacitor can be shortened, and a peak hold circuit that can follow the input signal level at high speed can be created with a simple circuit configuration and a small capacity. Can be obtained by charging power.

Note that O is an output circuit having a high input impedance for outputting the peak hold voltage Vpk held by the voltage holding capacitor C, and D is the charge held by the voltage holding capacitor C in response to the discharge signal P. the current 1
This is a discharge circuit that discharges as d.

(Embodiment) FIG. 2 is a circuit diagram showing an embodiment of the peak hold circuit according to the present invention, in which the peak hold circuit shown as 8 in FIG. 4 is provided corresponding to each of the balanced transmission lines. Although it is equivalent to one of the peak hold circuits, it is not used only for this purpose (-- it goes without saying that it can be used for boat fishing to hold the peak value of the input signal do not have.

For example, transistors Q and Q2 to which an input signal Vs, which is a read signal read from the magnetic recording medium described with reference to FIG. It is connected to a constant current source K in parallel with the transistor Q3 to which the output peak voltage VPK of is applied, and these transistors Ql, Qt and the transistor Q3 constitute a differential amplifier.

Transistors Q4 and Q are input-side and output-side transistors that constitute a current mirror circuit, respectively,
Its emitter is connected to the power supply ■ through resistor R0 and resistor R2.
Cc, and the output current of this transistor Q5 supplies a charging current that charges the terminal voltage of the voltage holding capacitor C to the peak voltage of the input signal Vs.

The transistor Q6 and the transistor Q7 constitute a differential amplifier, and when the peak pulse shown in FIG. 5 (i) generated at the peak of the input signal is input to the base of the transistor Q6, the The other transistor Q, whose collector is connected to the capacitor C, is made conductive to discharge the charge stored in the capacitor C through the transistor Q3.

Transistors Q8 and Q are an output circuit configured as a Darlington circuit to increase input impedance, and the base of transistor QB on the input side is connected to the voltage holding capacitor C, and the emitter side of transistor Q is connected to the base of transistor QB on the input side. A peak voltage corresponding to the terminal voltage of the voltage holding capacitor C is outputted from the voltage holding capacitor C, and this peak voltage is supplied to the base of the transistor Q3, and is also applied to the level discrimination circuit in the data separator shown in FIG. ) is supplied, for example, as a slice level on the positive side of the slice level indicated by the dashed line.

Note that the slice level on the negative side of the opposite polarity in FIG. 5(f) is configured as a balanced circuit as described in FIG. It is supplied from the same peak hold circuit as above.

In the above circuit configuration, it is
and I2, the charging current that charges the capacitor C from the current mirror circuit is Ic, the discharge current of the capacitor C flowing through the transistor Q5 is Id, the current flowing through the transistor Q3 is Il, the current flowing through the constant current circuit K is I, Letting PP be the inverted pulse of the peak pulse that occurs during the period in which the input signal has a peak, the following equation holds true.

I = II +I3 − ・−■I
IR+=IzRz,'-Iz=It・Rl/RZ −・−
−−−■ From the values of these ■ and ■, the charging current of the voltage holding capacitor C is ■. is as shown in (1) to (3) below.

(When 11PP is H°, that is, when no peak pulse is input, the transistor Q is in the OFF state, so I,=I, and the following equation holds true.

Ic = 12 = II ・R+ /Rz-II
・R+ / Rz (2) When PP is “L”, that is, when a peak pulse exists, transistor Q5 is in the ON state, but when the read signal Vs is input, the transistor Q3 is in the OFF state, so the following formula holds true.

1, =13 =O Ic =Iz =I-R+ /Rz +31When PP is "L", that is, during the period when the peak voltage is held, the transistor Q is similarly in the ON state,
Furthermore, during peak hold when the input signal Vs is not input, the transistor Q3 is also in the ON state, so the following equation holds true.

I o = 13 = 1'--
-'---■ From the above formulas 1, 2, and 2, the charging current 1c and discharging current ID of the voltage holding capacitor C are as follows, respectively.

Ic = I-R+ / R2-- ID = 1
−−−− ■Therefore, even if the current I from the constant current source is small, R+ > R2
By setting it as , the charging current IC of the voltage holding capacitor C can be increased.

In this way, by using a current mirror circuit on the charging side, even if the current capacity of the charging power source is small, the time to charge the voltage holding capacitor C can be shortened, and a peak hold output that sufficiently follows the input signal Vs can be obtained. be able to.

To explain the operation of the embodiment shown in FIG. 2, in the initial state, the inverted peak pulse PPO value is at a positive potential of, for example, 4.5 cm, so the transistor Q6 becomes conductive and current flows, so that the transistor Q6 The transistor Q7, which is differentially connected to the transistor Q7 and has a voltage of 1.5 V applied to its base, is in a cut-off state.

Since the value of the input signal Vs is "0", no current flows through the transistor Q1, and since the transistor Q2 becomes conductive due to the voltage of 0.2■ applied to its base, the transistor Q2 and the transistor Q4 are A current 2 flows through the transistor Q, and a voltage is applied to the base of the transistor Q through the resistor R1R3, so that the transistor Q5 becomes conductive.

As a result, the current I2 passing from the power supply Ecc through the resistor R2 and this transistor Q is used as a charging current Ic, and the terminal voltage of the voltage holding capacitor C is set to the transistor Q2.
The battery is charged until it becomes equal to the DC voltage Vd of 0.2 V which is the input of the battery.

The voltage of this voltage holding capacitor C is applied to the transistor Q8 and the transistor Q whose emitter follower is connected to this transistor Qll.

A peak hold voltage PK is output from the emitter of the voltage VPK to the level discrimination circuit 71 shown in FIG. 4 and is also applied to the base of the transistor Q3. With this delay, the DC voltage Vd, which is the input of the transistor Q2, and the transistor Q
The peak hold voltages V□, which are the base potentials of , become equal, resulting in an equilibrium state.

Here, the input signal Vs input to the transistor Q1
When the level of Vd rises above the DC voltage Vd, the current I flowing through this transistor Q1 increases, and thereby the current I2 flowing through the transistor Q also increases, but the inverted peak pulse PP still maintains 4.5V. Therefore, the transistor Q7 remains cut off, and the transistor Q of the current mirror circuit continues to charge the voltage holding capacitor C with the current 1c from the power supply Ecc, and the terminal voltage of the transistor Q11. Peak hold voltage V through Q9
pk is output to the level discrimination circuit and fed back to the base of the transistor Q, so that its potential becomes equal to the input signal voltage, which is the input signal, and is balanced.

As described above, the charging current Ic flowing from the resistor R2 of the current mirror circuit through the transistor Q5 becomes Ic=It ・R+ / Rz with respect to the current I flowing through the transistor Q2, as shown in the equation (2) above. Since R,>R, the current becomes extremely large, which has the effect of high followability to the input signal.

Next, when the voltage of the input signal Vs falls below the terminal voltage of the voltage holding capacitor C, that is, the base potential of the transistor Q3, the current flowing from the power supply Vcc to the transistor Q3 via the transistor Q6 increases, so the current flowing through the transistors Q, Q2 becomes Reduced current mirror circuit transistor Q.

Since the charging current 1c is cut off, the charging current 1c is also cut off, but since the transistor Q6 remains conductive as described above, the transistor Q7 is also cut off, so the charge held by the voltage holding capacitor C is transferred to the transistor The voltage is held in a state where the voltage is simply discharged through the high input impedance of Q8.

When the peak of the input signal is detected and the inverted peak pulse PP becomes 0.4 V, this inverted peak pulse PP is connected as a differential circuit with the transistor Q6 applied to the base, and a voltage of 1.5 V is applied to the base. Since the transistor Q to which voltage is applied becomes conductive, the voltage holding capacitor C
The charge held by is discharged through transistor Q3 and constant current circuit K, but the discharge current is Ic = Io ・R+ /Rz ■ゎ =I, ・Rz/R from the above formulas ① and ②, and R , >R2, so the current is significantly smaller than the charging current.

If a dropout occurs in the input signal Vs, the peak voltage of the input signal Vs will be smaller than the previous peak voltage, so the terminal voltage of the voltage holding capacitor C will rapidly drop due to discharge at each peak pulse. When the dropout disappears, the voltage holding capacitor C is charged by a large current due to the use of the current mirror circuit Ic-B ・R+/Rz, as shown in Part II above, so the terminal voltage of this capacitor A certain peak voltage ■□ follows the input signal and recovers rapidly.

FIG. 4 is an operating waveform diagram of the embodiment shown in FIG. 2, in which the fa1 diagram shows the input signal Vs that is the input to the transistor Q1, the DC signal Vd that is the input to the transistor Qz, and the peak hold output Vpk. (bJ figure is an inverted peak pulse that is an inversion of the peak pulse generated by another circuit at the peak of the input signal, (C) to (e
) The figure shows the current shown in FIG. 2, and the figure (f) shows the charging and discharging current of the voltage holding capacitor C. In this figure, the recording period of one bit is 1028 μs, and the values of each voltage are shown as examples, but since the operation has been described above, the details will be omitted.

〔Effect of the invention〕

As explained above, since the peak hold circuit according to the present invention has a current mirror circuit on the input side of the voltage holding capacitor, not only does the charging speed of the voltage holding capacitor become faster, but also the capacity of the current source is small. The special effect of being able to finish is achieved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the principle of the present invention, Fig. 2 is a circuit diagram showing the configuration of an embodiment of the invention, Fig. 3 is a waveform diagram showing the operation of the embodiment of Fig. 2, and Fig. 4 is a A block diagram showing the configuration of a DDNRZI data demodulation circuit suitable for using the peak hold circuit of the present invention. FIG. 5 is an operational waveform diagram of the demodulation circuit of FIG. 4. Patent applicant: Fujitsu Limited Principle diagram Figure 1 Embodiment Figure 2

Claims (1)

[Claims] a voltage holding capacitor that holds the peak value of the input signal;
In a peak hold circuit comprising an output circuit having a high input impedance for outputting the terminal voltage of the capacitor, and a discharge circuit for discharging the capacitor,
A peak hold circuit characterized in that the input signal is supplied to the voltage holding capacitor via a current mirror circuit.