JPH0224572A - Peak hold circuit - Google Patents

Abstract

PURPOSE:To make a peak hold signal follow an input signal precisely by setting the peak hold signal at a direct-current potential in a reset state and by diminishing a difference potential from a peak hold input potential. CONSTITUTION:During a period when a reset signal (a) is at a high potential (a potential enough to turn ON a transistor Tr 4 sufficiently), the collector of the Tr 4 is kept at a potential being equal to a direct-current potential Vb to which the base thereof is connected. A capacitor 3 is charged or discharged so that the potential of an input terminal of an emitter follower circuit 5 connected to the collector of the Tr 4 be in accord with the potential Vb, and an output signal (c) is kept at the potential Vb irrespective of an input signal (b), as shown by a broken line. When the signal (a) changes to be at a low potential from this state, the Tr 4 turns OFF, and a potential at the node of a diode 2 and the capacitor 3 turns to be a value according with the signal (b) since the capacitor 3 is charged when the signal (b) changes to a value larger than the one of the preceding potential. By this constitution, a peak hold signal is made to follow the signal (b) precisely.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a peak hold circuit that holds the peak value of a human input signal.

BACKGROUND OF THE INVENTION The configuration of a conventional peak hold circuit will be explained with reference to FIG.

A conventional peak hold circuit includes a first amplifier circuit l having an inverting input terminal and a non-inverting input terminal, a diode 2 connected to the output of the first amplifier circuit, and a diode 2 and a first reference. A capacitor 3 inserted between the potentials,
a second amplifier circuit 5 connected to a connection point between the diode 2 and the capacitor 3; and a reset circuit that sets an input terminal of the second amplifier circuit to a first reference potential;
The output of the amplifier circuit is connected to the inverting input terminal of the second amplifier circuit.

Here, when a reset signal as shown in FIG. 4(a) is input from the reset input terminal 8 and an input signal as shown in FIG. 4(b) is input from the input terminal 6, the output signal (C) is ,
During the reset period, it becomes the first reference potential, and during the reset circuit period, it becomes a waveform that holds the peak value of the input signal.

Problems to be Solved by the Invention The above-mentioned conventional peak hold circuit has a large difference between the voltage value of the peak hold signal immediately after reset release and the voltage value of the input signal, so it has difficulty following the input signal. There were drawbacks that made it worse.

The present invention aims to solve the problems that may occur with the above-mentioned conventional circuits. (1) A peak hold circuit that can obtain a peak bold signal with good followability for an input signal superimposed on a DC potential of 5. It provides:

Means for Solving the Problems The peak hold circuit of the present invention includes a first amplifier circuit having an inverting input terminal that inverts the curvature of a human input signal and a non-inverting input terminal that does not invert the characteristic, and an output of the first amplifier circuit. a capacitor inserted between the diode and the first reference potential, a second Jt1 width circuit with a large input impedance connected to the connection point of the diode and the capacitor, and an external a reset circuit that sets the input terminal of the second amplifier circuit to a second reference potential in response to a reset signal, and connects the output of the second amplifier circuit to the inverting input terminal of the first amplifier circuit. It is connected to.

When a reset signal is input from the reset input terminal of the action peak hold circuit, the reset circuit enters the reset state, the input terminal of the second amplifier circuit is reset to the second reference potential (7), and the output signal is is fixed at the second reference potential. After that, when the reset signal is released,
The output signal changes from a state fixed to the second reference potential to a waveform in which the peak value of the input signal is held.

Example Below, regarding a peak hold circuit according to an example of the present invention,
This will be explained with reference to the drawings.

As shown in FIG. 1, there is an amplifier circuit 1 having an inverting input terminal and a non-inverting input terminal, a diode 2 connected to the output of the amplifier circuit 1, and a capacitor 3 inserted between the diode 2 and the ground. and an emitter follower circuit 5 connected to the connection point between the diode 2 and the capacitor 3.
and a transistor 4 which sets the input terminal of the emitter follower circuit 5 to a DC potential of {circle around (2)} in response to an external reset signal, and the output terminal 7 of the emitter follower circuit 5 is connected to the inverting input terminal of the amplifier circuit, The transistor 4
The collector of is biased to V, a direct 7N potential 9.

Next, to explain the operation in detail, as shown in Figure 2,
The reset signal (a) is at High level (transistor 4
During the period when the collector of the transistor 4 is connected to the base and is kept at a potential approximately equal to the DC potential 5, the collector of the transistor 4
The potential of the input terminal of the emitter follower circuit 5 connected to the collector of is ■.

The charging and discharging of the capacitor 3 is performed so that the output signal (C) matches the input signal [
The potential is maintained at ■, regardless of whether the

From this state, the reset signal (a) is I, ow potential (○
, potential), the transistor 4 turns off, and the potential at the connection point between the diode 2 and the capacitor 3 becomes
When the input signal (c) changes to a value larger than the previous potential, capacitor 3 is charged and becomes a value that matches the input signal (b), and when the input signal (b) changes to a value smaller than the previous potential. Since there is no discharge path for the capacitor 3, the peak value of the input signal (b) is held, and it functions as a peak hold circuit.

After that, when the reset signal (a) becomes Hrgh potential again, the transistor 4 is turned on, and the transistor 4 is turned on.
The collector potential of is ■, and the output signal (C) is ■,
After that, the reset signal (a) becomes L again.
owit, and when the reset is released, the output signal (C) becomes a signal that holds the peak value of the input signal (1) again.6 As described above, when the reset state B (reset signal is High
h potential), the output signal (C) is kept at the potential of ■5, which is the potential on which the input signal is superimposed, and when the reset is released, it starts to follow the input signal from the potential of ■. Therefore, it is possible to minimize the potential difference between the output signal (C) and the input signal (b) immediately after reset release, and it is possible to follow the input signal with higher accuracy.

Effects of the Invention According to the present invention, when holding the peak of an input signal superimposed on a potential of (1), since the peak hold signal is at a potential of approximately vb in the reset state, the input potential to be peak held is It is possible to obtain a peak hold circuit that can accurately follow the peak hold signal to the input signal immediately after the reset is released.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is an operation waveform diagram of FIG. 1, FIG. 3 is a circuit diagram showing an embodiment of a conventional peak hold circuit, and FIG. is an operating waveform diagram of FIG. 3. l...Amplification circuit, 2...Diode,
3... Capacitor, 4... Transistor, 5... Emitter follower circuit, 6...
...Input terminal, 7.Old...Output terminal 8...Reset input terminal, 9, Bias circuit. Name of agent: Patent attorney Shigetaka Awano Figure 3 Figure 4

Claims (2)

[Claims] (1) a first amplifier circuit having an inverting input terminal that inverts the polarity of an input signal and a non-inverting input terminal that does not invert the polarity of the input signal; a diode connected to the output of the first amplifier circuit; a capacitor inserted between a reference potential; a second amplifier circuit with a large input impedance connected to a connection point between the diode and the capacitor; and an input terminal of the second amplifier circuit in response to an external reset signal. A peak hold circuit comprising: a reset circuit that sets a second reference potential; and an output of the second amplifier circuit is connected to an inverting input terminal of the first amplifier circuit. (2) The peak hold circuit according to claim 1, wherein the second reference potential is approximately the DC potential of the AC input signal of the first amplifier circuit.