JPS6215958B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit that can sample and hold an input signal with large amplitude changes.

FIG. 1 is a circuit diagram showing a conventional sample and hold circuit. The base of a transistor 2 is connected to the input terminal 1. The collector of transistor 2 is connected to power supply terminal 14 . A constant current source 3 and one terminal of a resistor 4 are connected to the emitter of the transistor 2. The other terminal of constant current source 3 is grounded. The other terminal of resistor 4 is connected to the base of transistor 5. The collector of transistor 5 is connected to power supply terminal 14 . Transistor 6 and transistor 7
constitutes a differential amplification section, and the base of transistor 5 is connected to the collector of transistor 6. One terminal of a base bias power supply 8 is connected to the base of the transistor 6. The other terminal of base bias power supply 8 is grounded. The emitter of transistor 6 is connected to one terminal of constant current source 9. The other terminal of constant current source 9 is grounded. The emitter of transistor 5 is connected to the collector of transistor 7. The base of transistor 7 is connected to sampling pulse input terminal 10. The emitter of transistor 7 is similar to transistor 6,
It is connected to one terminal of constant current source 9. A hold capacitor 1 is connected to the connection portion 11 between the emitter of the transistor 5 and the collector of the transistor 7.
One terminal of 2 and the output terminal 13 are connected. The other terminal of the hold capacitor 12 is grounded. Constant current source 3 is transistor 2
This is to stabilize the operation. Constant current source 9 is also used to stabilize the operation of transistor 6 and transistor 7. Further, transistor 2 and transistor 5 each constitute an emitter follower, and their voltage amplification factor is 1.
It is.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to FIG. FIG. 2 is a schematic diagram showing signal waveforms at each part of FIG. 1. Note that in the following explanation, the voltage drop between the base and emitter of the transistor will be ignored for convenience of explanation. An input signal Vi to be sampled and held is input to the input terminal 1. This input signal Vi is, for example, a tracking signal for controlling an arm along a groove in a video disc device. This input signal Vi is input to the base of a transistor 5 via a transistor 2 and a resistor 4. Sampling pulse input terminal 10
A sampling pulse Vp is input to. This sampling pulse Vp is, for example, a horizontal synchronization pulse. This sampling pulse Vp
The relationship between the voltage level and the level of the bias voltage _V1 of the base bias power supply 8 is shown in FIG. That is, the level of the bias voltage _V1 is between the "H" level and the "L" level of the sampling pulse Vp. First, when the sampling pulse Vp becomes "H", the base potential of transistor 7 becomes higher than the base potential of transistor 6, transistor 7 is turned on, and the emitter follower circuit composed of transistors 5 and 7 is also turned on. However, the input signal Vi that has been input to the base of the transistor 5 is input to the hold capacitor 12 via the transistor 5, and is simultaneously charged to the hold capacitor 12 and output to the output terminal 13 as an output signal Vo. Next, when the sampling pulse Vp becomes “L”,
The base potential of transistor 6 becomes higher than the base potential of transistor 7, and transistor 6 is turned on. When transistor 6 is turned on, current from power supply terminal 14 flows through transistor 2 , resistor 4 , and transistor 6 . The value of resistor 4 is
Since the potential at the base of transistor 5 due to the voltage drop at this time is set to be lower than in any case of input signal Vi, transistor 5 is reverse biased and turned off. As a result, the charge/discharge path for the charges accumulated in the hold capacitor 12 when the sampling pulse Vp is "H" is cut off, and the potential of the hold capacitor 12 is held. Furthermore, again the sampling pulse Vp
When V becomes "H", the emitter follower circuit composed of transistors 5 and 7 operates as described above, and the input signal Vi is applied to the hold capacitor 12. At this time, if the potential of the output signal Vo immediately before being sampled is higher than the potential of the input signal Vi at the time of sampling, the charge in the hold capacitor 12 is reduced by the transistor 7.
and discharged through the constant current source 9, and conversely, if the potential is lower than the input signal Vi, the hold capacitor 12 is charged by the transistor 5, and as a result, the potential of the output signal Vo during sampling becomes equal to the potential of the input signal Vi. . This output signal Vo
is used, for example, in the drive circuit of the arm of the video disc device.

However, the above is a case where the amplitude change of the input signal Vi is not very large, and when the amplitude change of the input signal Vi is large, this conventional circuit
The drawback was that it did not operate accurately. This will be further explained with reference to FIG. Fourth
The figure is a schematic diagram showing signal waveforms at various parts in FIG. 1 when the amplitude change of the input signal is large. If the current flowing through the constant current source 9 is I ₂ and the capacitance of the hold capacitor 12 is C, then the output signal V ₀
The rate of change in is expressed as I ₂ /C. This I ₂ /C
The larger the value of , the better the ability to follow the amplitude change of the input signal Vi. However, the value of the current I ₂ has a limit due to the capacitance of the transistor 6 and the transistor 7, and there is also a limit due to the desire not to increase power consumption, so it cannot be made very large. On the other hand, the capacitance C of the hold capacitor 12
However, if this value is made small, there will be a limit to the time that can be held, and input signals with a large period cannot be held accurately, so it cannot be made very small. Therefore, when the amplitude change of the input signal Vi is large, the output signal V ₀ will look like the dotted line in Figure 3 if it is ideally held, but in reality it will look like the solid line in Figure 3, It was causing an error dV ₀ .

The present invention has been made to eliminate the drawbacks of the conventional circuits described above, and an object of the present invention is to provide a sample-and-hold circuit that has good followability for input signals with large amplitude changes.

In summary, the present invention is a sample and hold circuit including an emitter follower circuit that forcibly charges and discharges a hold capacitor.

Embodiments of the present invention will be described below based on the drawings.

FIG. 4 is a circuit diagram showing an embodiment of the present invention. The base of the transistor 15 and the base of the transistor 16 are connected to the input terminal 1. The collector of transistor 15 is grounded. The emitter of transistor 15 is connected to the collector of transistor 6 of transistor 6 and transistor 7 forming a differential amplifier similar to the conventional circuit described above. transistor 1
The collector of 6 is connected to the power supply terminal 14.
The emitter of transistor 16 is connected to the collector of transistor 7. As in the conventional circuit described above, a base bias power supply 8 is connected to the base of the transistor 6. transistor 6
A constant current source 9 is connected to the emitter of the transistor 7 and the emitter of the transistor 7. The base of transistor 7 is connected to the sampling pulse input terminal. The emitter of transistor 15 and the collector of transistor 6 are connected to power supply terminal 14 via resistor 17 . transistor 1
The emitter of transistor 6 and the collector of transistor 7 are connected to power supply terminal 14 via resistor 18 . Further, the emitter of the transistor 15 is connected to the base of the transistor 19.
Transistor 2 is also connected to the emitter of transistor 16.
0 base is connected. transistor 19
The collector of is connected to the power supply terminal 14. Emitter of transistor 19 and transistor 2
The emitters of 0 are connected at a connecting portion 21. The collector of transistor 20 is grounded. A hold capacitor 12 is connected between the connecting portion 21 and the ground. The connection part 21 is connected to the output terminal 13. transistor 15,1
6, 19, and 20 each constitute an emitter follower, and their voltage amplification factors are 1.

Next, the operation of the circuit shown in FIG. 4 will be explained. The relationship between the level of the sampling pulse input Vp and the level of the bias voltage _V1 and the magnitude of the current _I2 are the same as in the conventional circuit described above. Input terminal 1
The input signal Vi input to the transistor 15
and the base of transistor 16, and is further applied to the base of transistor 19 via transistor 15. First, when the sampling pulse Vp becomes "H", the transistor 7 is turned on as described above, so the emitter follower composed of the transistor 16 and the transistor 7 works, and the input signal Vi
is connected to transistor 2 via transistor 16.
Given on a base of 0. As described above, since the input signal Vi is also applied to the base of the transistor 19, this turns on the transistor 19 and the transistor 20, and the input signal Vi is supplied to the hold capacitor 12. At this time, if the potential of the output signal _V0 immediately before being sampled is higher than the potential of the input signal Vi at the time of sampling, the emitter follower of the transistor 20 discharges the charge of the hold capacitor 12, and conversely, the potential of the input signal Vi is higher than the potential of the input signal Vi. If low, transistor 19
The hold capacitor is charged by the emitter follower. Here, the base currents of transistor 19 and transistor 20 are respectively I _B 19
and I _B 20, and the common emitter current amplification factors of transistor 9 and transistor 20 are h _FE 19 and h _FE 20, respectively, then the charging current of the hold capacitor 12 is h _FE 19·I _B 1
9, and the discharge current of the hold capacitor 12 becomes h _FE 20·I _B 20. Here, if we compare with the conventional sample and hold circuit, the base current I
Since _B 19 and I _B 20 are the current I ₂ ,
The charging and discharging currents of the hold capacitor 12 are h _FE 19·I ₂ and h _FE 20·I ₂ , respectively.
Here, as an example, if the transistor 19 and the transistor 20 are transistors in an IC (integrated circuit), h _FE is approximately 50 each, so the charging/discharging current of the hold capacitor 12 is
50I ₂ , which means it has 50 times the charging and discharging capacity compared to conventional sample and hold circuits. Therefore, the charging/discharging time during sampling can be significantly shortened, and the output signal V ₀ also draws an ideal curve as shown by the dotted line in FIG.

As described above, according to the present invention, it is possible to obtain a sample-and-hold circuit that has good followability for input signals with large amplitude changes and can sample and hold the input signals with high accuracy.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional sample and hold circuit. FIG. 2 is a schematic diagram showing signal waveforms at each part of FIG. 1. FIG. 3 is a schematic diagram showing signal waveforms at various parts in FIG. 1 when the amplitude change of the input signal is large. FIG. 4 is a circuit diagram showing an embodiment of the present invention. In the figure, 6, 7, 15, 16, 19, 20
is a transistor, 8 is a base bias power supply, 9 is a constant current source, 12 is a hold capacitor, 17,
18 is a resistor.

Claims (1)

[Claims] 1. First and second transistors whose input sections are connected to each other and into which an input signal to be sampled and held is input; 1 and a second output section, a bias power supply is input to the first input section, a sampling signal is input to the second input section, and the first output section is provided with the first output section. is connected to the output part of the transistor,
a differential amplifier whose second output section is connected to the output section of the second transistor; a third transistor whose input section is connected to the output section of the first transistor; and a third transistor whose input section is connected to the output section of the first transistor. a fourth transistor connected to the output part of the second transistor, the output part of the third transistor and the output part of the fourth transistor are connected to each other, and the connection part and the fourth transistor are connected to each other. further comprising a capacitor connected between the ground, the third transistor forming a charging circuit for the capacitor, and the fourth transistor forming a discharging circuit for the capacitor; A sample and hold circuit that serves as an output section for the held output signal.