JPH07162277A - Pulse generator - Google Patents

Abstract

PURPOSE:To constitute a slew rate limiting circuit of transistors(TRs) having single polarity by inputting a differential signal for adjusting the slew rate of the slew rate limiting circuit to a differential amplifier and connecting 1st and 2nd capacitors between the positive or negative input terminal and negative or positive output terminal of the amplifier. CONSTITUTION:When an input signal to the slew rate limiting circuit 1 is turned from 'L' to 'H', the base voltage VB3, VB4 of two npn transistor TRs Q3, Q4 coincide with each other at a cross point of a differential input and the TRs Q3, Q4 display the function of a differential amplifier. Thereby the voltage VB3, VB4 are turned to 'H' potential. Then a TR Q1 is turned on and a current Ia from a current source I1 is allowed to flow as an emitter current. A TR Q2 is reversely biased and turned off and a current Ib from a current source I2 flows into a capacitor C2 to charge it. Thereby the collector voltage of the TR Q4 is boosted and a collector current IC4 is simultaneously reduced like a lamp. When IC4=0, charging ends and the base voltage VB4 of the TR Q4 is dropped. Collector current IC3 haS the relation of IC3=Ic-IC4. A differential amplifier 2 receives a differential signal controlled at its slew rate from the circuit 1 and generates a pulse waveform similar to the current IC4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator used in an LSI tester, a pulse generator, etc., and more particularly to a pulse generator in which a slew rate limiting circuit can be composed of transistors of one polarity. Is.

[0002]

2. Description of the Related Art A conventional pulse generator generates a pulse signal of a desired level by a differential amplifier which receives a differential signal from a differential signal source, and a pulse signal is generated by a slew rate limiting circuit provided in the subsequent stage of the differential amplifier. The slew rate of the signal was limited. Such a device is shown below. FIG. 3 is a diagram showing the configuration of a conventional pulse generator. In the figure, 2 is a differential amplifier which receives a differential signal and outputs a pulse signal of a desired level. And the differential amplifier 2 is
NPN transistors Q5 and Q6, constant current source I4 and resistor R
3 and 3. A slew rate limiting circuit 3 outputs a pulse signal in which the rising time and the falling time of the signal output from the differential amplifier 2 are limited. The slew rate limiting circuit 3 includes the NPN transistor Q7 and P
It is composed of an NP transistor Q8, current sources I5 and I6, and capacitors C3 and C4.

The operation of such a device will be described below.
First, the operation of the differential amplifier 2 will be described. When the differential signal is high level, the NPN transistor Q5 is turned on,
The NPN transistor Q6 is turned off, and no current flows through the resistor R3. The voltage VH is output from the differential amplifier 2. When the differential signal is low level, the NPN transistor Q5 is turned off, the NPN transistor Q6 is turned on, and the current Id of the constant current source I4 flows through the resistor R3. That is, the voltage drop of the resistor R3 due to the change of the collector current becomes the amplitude of the pulse signal. Then, the high level of the pulse signal becomes "VH" and the low level becomes "VH-Rc × I".
Here, Rc is the resistance value of the resistor R3, and Id is the current value of the constant current source I4.

Next, the operation of the slew rate limiting circuit 3 will be described. When the pulse signal from the differential amplifier 2 rises, a current flows between the collector and the emitter of the NPN transistor Q7, and the capacitor C3 is charged. At this time,
No current flows between the collector and emitter of the PNP transistor Q8, and the capacitor C4 is charged by the current from the current source I6. As a result, the rise time of the output of the slew rate limiting circuit 2 is delayed. And
When the pulse signal from the differential amplifier 2 falls, NPN
No current flows between the collector and emitter of the transistor Q7, and current flows from the capacitor C3 to the current source I5 and is discharged. At this time, a current flows between the collector and emitter of the PNP transistor Q8, and the capacitors C4 to N
A current flows through the PN transistor Q8 and is discharged. As a result, the output of the slew rate limiting circuit 3 has a slow fall time. Here, the slew rate can be adjusted by adjusting the amount of current of the current sources I5 and I6.

[0005]

In the case of such a configuration, there is a problem in that only one transistor of the slew rate limiting circuit 3 has to use transistors of different polarities.

An object of the present invention is to realize a pulse generator in which a slew rate limiting circuit is composed of transistors of one polarity.

[0007]

According to the present invention, in a pulse generator for generating a pulse by a differential signal, a drive circuit for inputting the differential signal, and a differential amplifier for inputting the output of the drive circuit. A first capacitor provided between a positive input terminal and a negative output terminal of the differential amplifier and charged by the drive circuit based on the differential signal; and a negative input of the differential amplifier. A second capacitor provided between the end and the positive output end and charged by the drive circuit based on the differential signal, and a signal input to the differential amplifier is a differential signal. Is generated as a pulse. In addition, when one signal is at a high level, the other signal receives a pair of differential signals at a low level and generates a pulse in a pulse generator,
A first current source (I1) and a second current source (I2) are respectively connected to the emitters, and a collector is commonly connected to a first NPN transistor (Q1) and a second NPN transistor (Q2). A drive circuit (10) composed of
The third constant current source (I3) is connected to the emitter, and the emitters of the first NPN transistor and the second NPN transistor are respectively connected to the bases of the third NP.
A first differential amplifier (11) including an N-transistor (Q3) and a fourth NPN transistor (Q4),
A first capacitor (C1) provided between the collector and the base of the third NPN transistor, a second capacitor (C2) provided between the collector and the base of the fourth NPN transistor, and a fourth capacitor Current source (I4)
Is connected to the emitter and is composed of a fifth NPN transistor (Q5) and a sixth NPN transistor (Q6) whose bases are connected to the bases of the third NPN transistor and the fourth NPN transistor, respectively. Second
And a differential amplifier (2) for generating a pulse from the collector of the sixth NPN transistor. Further, the present invention is characterized in that the magnitudes of the currents of the first current source and the second current source are made variable to adjust the slew rate of the output pulse.

[0008]

In the present invention as described above, the differential signal is input to the drive circuit, and the first capacitor or the second capacitor is charged based on the differential signal. This operation changes the signal input to the differential amplifier. Then, a pulse is generated by using the signal input to the differential amplifier as a differential signal. In addition, the differential signal is input to the drive circuit and the first capacitor or the second capacitor is charged based on the differential signal. By this operation, the signal input to the first differential amplifier changes. The second differential amplifier is the first differential amplifier.
Pulse is generated by using the signal input to the differential amplifier as the differential signal. Furthermore, by changing the magnitude of the currents of the first current source and the second current source, the time for charging the first capacitor and the second capacitor changes. This change in time changes the slew rate of the output pulse.

[0009]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure,
Reference numeral 1 denotes a slew rate limiting circuit, which inputs a differential signal and outputs a differential signal having an adjusted slew rate to an input of a differential amplifier 2. Then, the differential amplifier 2 receives the differential signal from the slew rate limiting circuit 1 and generates a pulse. In the slew rate limiting circuit 1, 10 is a drive circuit to which a differential signal is input. A differential amplifier 11 is connected to the drive circuit 10. Then, the signal input to the differential amplifier 11 is output to the differential amplifier 2 as a differential signal. C1 is a first capacitor, which is provided between the positive input terminal and the negative output terminal of the differential amplifier 11. C2 is a second capacitor, which is provided between the negative input terminal and the positive output terminal of the differential amplifier 11. In the drive circuit 10, I1 and I2 are first and second
One end of the current source is connected to -5V level, and the amount of current can be adjusted. Q1 is the first emitter follower NP
In the N-transistor, the other end of the current source I1 is connected to the emitter. Q2 is an NPN transistor which is a second emitter follower, and the other end of the second current source I2 is connected to the emitter. In the differential amplifier 11, the bases of the NPN transistors Q3 and Q4 are used as the positive input terminal and the negative input terminal, respectively, and the emitters of the NPN transistors Q1 and Q2 are respectively connected. The emitter is connected to one end of the constant current source I3, and the collectors are connected to the resistors R1 and R2, respectively.
One end of is connected to serve as a negative output terminal and a positive output terminal. The other end of the constant current source I3 is connected to the -5V level, and the resistor R
The other ends of 1 and R2 are grounded. In the differential amplifier 2, the bases of the NPN transistors Q3 and Q4 are connected to the bases of the NPN transistors Q5 and Q6, respectively, and one end of the constant current source I4 is connected to the emitter thereof. The other end of the constant current source I4 is connected to the -5V level. NPN
The collector of the transistor Q5 is connected to the voltage value VH level, and the collector of the NPN transistor Q6 has a resistance R
3 is connected to one end. The other end of the resistor R3 has a voltage value V
It is connected to H level. Then, the output of the collector of the NPN transistor Q6 is output as a pulse.

The operation of such a device will be described below.
FIG. 2 is a timing chart showing the operation of the device of FIG. First, the operation of the slew rate limiting circuit 1 will be described. In the initial state, the differential signal is low level (for example,
-1.8V). At this time, the NPN transistor Q
Since the emitter of 1 is low and the emitter of NPN transistor Q2 is high, the base voltage VB3 of NPN transistor Q3 and the base voltage V of NPN transistor Q4 are
B4 is VB3 <VB4. That is, the NPN transistor Q3 is turned off and the NPN transistor Q4 is turned on. As a result, all the current Ic of the constant current source I3 flows between the collector and the emitter of the NPN transistor Q4.

At time t1, it is assumed that the differential signal transits from low level to high level (for example, -0.9V). At the differential input cross point, the base voltages VB3 and VB4 of the NPN transistors Q3 and Q4 are the same, and the NPN transistors Q3 and Q4 enter the active region to exert the function of differential amplification. As a result, the base voltages VB3 and VB4 both become high-level potentials, and both move slightly. Therefore, the NPN transistor Q1 is turned on, and the current Ia of the current source I1 flows as the emitter current. Then, the NPN transistor Q2 is reverse-biased and turned off, and the current Ib of the current source I2 is entirely converted to the capacitor C2.
And the capacitor C2 is charged. As a result, NP
The collector voltage of the N-transistor Q4 rises like a ramp as the capacitor C2 is charged. At the same time, the collector current IC4 of the NPN transistor Q4 decreases like a ramp. Eventually, when IC4 = 0, charging is completed,
The base voltage VB4 of the NPN transistor Q4 starts decreasing toward the low level. Since the operation of the NPN transistor Q3 is a differential amplification operation with the NPN transistor Q4, the collector current has a relation of IC3 = Ic-IC4.

Assuming that the time when the charging of the capacitor C2 is completed is t2, the charging time P1 is expressed by the following equation from time t1 to t2. P1 = Cb × ΔV / Ib (1) Cb: The capacitance ΔV of the capacitor C2 is the voltage change at the terminal of the capacitor C2 from time t1 to t2 and is represented by the following equation. ΔV = (Ic−Ib) × Rb (2) Rb: Resistance value of the resistor R2 If the equation (2) is substituted into the equation (1), P1 = (Ic−Ib) × Cb × Rb / Ib (3) Become. Expression (3) is a strict expression, but in many cases,
Since the current Ib is sufficiently smaller than the current Ic, it is treated as approximated as the following equation. P1≈Ic × Cb × Rb / Ib (4)

Similarly, it is assumed that the differential signal transits from the high level to the low level at time t3. At the cross points of the differential inputs, the NPN transistors Q3, Q
The base voltages VB3 and VB4 of No. 4 are the same, and the NPN transistors Q3 and Q4 enter the active region to exert the function of differential amplification. As a result, the base voltages VB3 and VB4 both remain at the high-level potential and move only slightly.
Therefore, the NPN transistor Q2 is on and the current source I2
Current Ib of the above is passed as an emitter current. And NPN
The transistor Q1 is reverse biased and turned off, and the current source I
All the current Ia of 1 flows into the capacitor C1, and the capacitor C1 is charged. As a result, the NPN transistor Q3
Collector voltage rises like a lamp as the capacitor C1 is charged. At the same time, the collector current IC3 of the NPN transistor Q3 decreases like a ramp. Eventually, IC3 =
When it reaches 0, charging is completed and the NPN transistor Q
The base voltage VB3 of 3 starts decreasing toward the low level. Since the NPN transistor Q4 operates differentially with the NPN transistor Q3, the collector current IC4 = Ic-IC3. At this time,
A current flows from the capacitor C2 to the NPN transistor Q4 and is discharged.

Assuming that the time when the charging of the capacitor C1 is finished is t4, the charging time P2 is expressed by the following equation from the time t3 to t4. P2 = Ca × ΔV ′ / Ia (5) Ca: The capacitance ΔV ′ of the capacitor C1 is a voltage change at the terminal of the capacitor C1 from time t3 to t4 and is represented by the following equation. ΔV ′ = (Ic−Ia) × Rb (6) Rb: Resistance value of the resistor R2 When the equation (6) is substituted into the equation (5), P2 = (Ic−Ia) × Ca × Ra / Ia (7) Becomes Expression (7) is a strict expression, but in many cases,
Since the current Ia is sufficiently smaller than the current Ic, the current Ia is approximated as in the following equation. P2≈Ic × Ca × Ra / Ia (8)

Next, the operation of the differential amplifier 2 will be described. N
The bases of the PN transistors Q5 and Q6 are NPs, respectively.
Since it is connected to the bases of the N transistors Q3 and Q4, the collector current has the following relationship. IC6 / IC5 = IC4 / IC3 (9) IC5, IC6: collector currents of NPN transistors Q5, Q6 In equation (9), the collector currents of NPN transistors Q5, Q6 are similar to the collector currents of NPN transistors Q3, Q4. It means that That is, the waveform output by the differential amplifier 2 becomes a voltage similar to the collector current IC4 of the NPN transistor Q4, and the slew rate is limited to the signal output by the differential amplifier 2. Then, the rising slew rate S1 and the falling slew rate S2 are as follows. S1 = Id × Rc / P1 (10) S2 = Id × Rc / P2 (11) Substituting equations (4) and (8) into equations (10) and (11) gives S1 = (Id × Rc / Ic × Rb × Cb) × Ib (12) S2 = (Id × Rc / Ic × Ra × Ca) × Ia (13) From equations (12) and (13), the rising slew rate S1 of the signal output by the differential amplifier 2 is determined by the current source I2.
Current Ib and falling slew rate S2 are
It can be seen that the current is determined by the current Ia. That is, the current source I
The slew rate can be adjusted by adjusting the currents of 1 and I2.

As described above, the slew rate limiting circuit can be configured with a single polarity transistor. If the slew rate limiting circuit is composed of NPN transistors, it is possible to generate pulses at high speed and with good waveform quality. That is, it is possible to eliminate problems such as long rise time or fall time due to the PNP transistor, deterioration of waveform quality such as occurrence of overshoot, and the like.

[0017]

The present invention has the following effects. According to the first aspect, the slew rate limiting circuit can be configured by a transistor having one polarity. Claim 2
According to the above, since the pulse generator is composed of the NPN transistor, it is possible to generate a pulse with high waveform quality at high speed. According to the third aspect, since the magnitudes of the currents of the first current source and the second current source are made variable, the slew rate of the pulse can be adjusted.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the device of FIG.

FIG. 3 is a diagram showing a configuration of a conventional pulse generator.

[Explanation of symbols]

1 Slew rate limiting circuit 2,11 Differential amplifier 10 Driving circuit C1, C2 Capacitor I1, I2 Current source I3, I4 Constant current source Q1, Q2, Q3, Q4, Q5, Q6 NPN transistor

Claims (3)

[Claims] 1. A pulse generator for generating a pulse by a differential signal, a drive circuit for inputting the differential signal, a differential amplifier for inputting an output of the drive circuit, and a positive amplifier for the differential amplifier. A first capacitor provided between the input end and the negative output end and charged by the drive circuit based on the differential signal; and a negative input end and a positive output end of the differential amplifier. A second capacitor provided between the capacitors and charged by the drive circuit based on the differential signal; and generating a pulse using the signal input to the differential amplifier as a differential signal. Pulse generator. 2. A pulse generator that generates a pulse by receiving a pair of differential signals in which one signal is at a high level and the other signal is at a low level, and generates a pulse in the first current source (I1) and the second current source (I1). A current source (I2) of which is connected to the emitter, respectively, and a collector of which is commonly connected, a drive circuit (10) including a first NPN transistor (Q1) and a second NPN transistor (Q2), The third constant current source (I3) is connected to the emitter, and the emitters of the first NPN transistor and the second NPN transistor are respectively connected to the bases of the third NP.
A first differential amplifier (11) composed of an N-transistor (Q3) and a fourth NPN transistor (Q4), and a first capacitor (provided between the collector and base of the third NPN transistor ( C1), a second capacitor (C2) provided between the collector and the base of the fourth NPN transistor, and a fourth current source (I4) are connected to the emitter, and the third capacitor
NPN transistor (Q5) and a sixth NPN transistor (Q5) whose bases are respectively connected to the bases of the NPN transistor and the fourth NPN transistor.
And a second differential amplifier (2) constituted by 6), and generating a pulse from the collector of the sixth NPN transistor. 3. The pulse generator according to claim 2, wherein the slew rate of the output pulse is adjusted by varying the magnitudes of the currents of the first current source and the second current source.