JPS58185096A - Sample holding circuit - Google Patents

Abstract

PURPOSE:To ensure the sample holding of a large input signal, by providing the 1st and 2nd transitors(TRs) to which the input signal to receive the sample holding is inputted, a differential amplifier, a capacitor, the 3rd and 4th TRs forming a charging/discharging circuit of the capacitor, and an output part respectively. CONSTITUTION:An input signal Vi given from an input terminal 1 turns on TRs 19 and 20 via TRs 15 and 16. When a smapling pulse VP is set at ''H'', a TR7 is turned on to actuate an emitter follower consisting of TRs 16 and 7. Then the signal Vi is supplied to a holding capactior 12. In this case, if the potential Vo of the output signal obtained immediately before sampling is higher than the signal Vi, the electric charge of a holding capacitor 12 is discharged. While the electric charge of the capacitor 12 is charged when the Vo is lower than the Vi. This ensures the sample holding with good follow-up performance and high accuracy to an input signal having a big change of amplitude.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit that can sample an input signal with large amplitude changes.

FIG. 1 is a circuit diagram showing a conventional sample and hold circuit. The base of a transistor 2 is connected to the input terminal 1. The collector of transistor 2 is connected to power supply terminal 14 . A constant current source 3 and one terminal of a resistor 4 are connected to the emitter of the transistor 2. The other terminal of constant current I13 is grounded. The other terminal of resistor 114 is connected to the base of transistor 5. The collector of transistor 5 is connected to power supply terminal 14 . Transistor 6 and transistor 7 constitute a differential amplifier, and the base of transistor 5 is connected to the collector of transistor 6. One terminal of a base bias power supply 8 is connected to the base of the transistor 6.

The other terminal of the base bias voltage l18 is grounded. The emitter of transistor 6 is connected to one terminal of constant current 1i9. The other terminal of constant current II9 is grounded. The emitter of transistor 5 is connected to the collector of transistor 7. The base of transistor 7 is connected to sampling pulse input terminal 10. Similar to transistor 6, the emitter of transistor 7 is connected to one terminal of constant current 119. A connection portion 11 between the emitter of the transistor 5 and the collector of the transistor 7 is connected to one terminal of a hold capacitor 12 and an output terminal 13 .

The other terminal of the hold capacitor 12 is grounded. The constant current source 3 is for stabilizing the operation of the transistor 2. The constant current 19 is also for stabilizing the operation of the transistor 6 and the transistor 7. Further, transistor 2 and transistor 5 each constitute an emitter follower, and their voltage amplification factor is 1.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to FIG. FIG. 2 is a schematic diagram showing signal waveforms at each part of FIG. 1. Note that in the following description, the voltage drop between the base and emitter of the transistor will be ignored for convenience of explanation.

An input signal vi to be sampled and held is input to an input terminal 1. This input signal v1 is, for example, a tracking signal for controlling an arm along a groove in a video disc device. This input signal Vi passes through a transistor 2 and a resistor 4 to a transistor 5.
is entered on the basis of A sampling pulse Vp is input to the sampling pulse input terminal 10. This sampling pulse Vp is, for example, a horizontal synchronization pulse. The relationship between the voltage level of this sampling pulse vp and the level of the bias voltage (2) of the base bias power supply 8 is shown in FIG. That is, the bias voltage V,
The level of is between the "H" level of the sampling pulse vp and the LII level. First, when the sampling pulse vp becomes "H", the base potential of the transistor 7 becomes higher than the base potential of the transistor 6, and the transistor 7 is turned on, and along with that, the Emitsutaf lower circuit consisting of transistor 5 and transistor 7 is also turned on,
Input signal v1 input to the base of transistor 5
is connected to the hold capacitor 12 via the transistor 5.
, and simultaneously charges the hold capacitor 12 and outputs it to the output terminal 13 as an output signal vO. Next, when the sampling pulse vp becomes "L", the base potential of the transistor 6 becomes higher than the base potential of the transistor 7, and the transistor 6 is turned on.

When transistor 6 is turned on, current from power supply terminal 14 flows through transistor 2. Flows through resistor 4 and transistor 6. The value of the resistor 4 is determined so that the potential at the base of the transistor 5 due to the voltage drop at this time is lower than in any case of the input signal V1, so the transistor 5 is reverse biased and turned off. As a result, the charge/discharge path for the charges accumulated in the hold capacitor 12 when the sampling pulse vp is H'' is cut off, and the potential of the hold capacitor 12 is held.

Furthermore, when the sampling pulse vp becomes "H" again, the emitter follower circuit composed of transistors 5 and 7 operates as described above, and the input signal @
vi is added to the hold capacitor 12. At this time, if the potential of the output signal 0 immediately before being sampled is higher than the potential of the input signal v1 at the time of sampling, the charge of the hold capacitor 12 is discharged through the transistor 7 and the constant current source 9, and conversely, the electric charge of the input signal vi If the potential is lower than the potential of the input signal @v1, the holding capacitor 12 is charged by the transistor 5, and as a result, the potential of the output signal @vO during sampling becomes equal to the potential of the input signal @v1. This output voltage @vO is used, for example, in the drive circuit of the arm of the video disc device.

However, the above is a case where the amplitude change of the input value @v1 is not very large, and this conventional circuit has the disadvantage that it does not operate accurately when the amplitude change of the input signal vi is large. This will be further explained with reference to FIG. FIG. 4 is a schematic diagram showing signal waveforms at various parts in FIG. 1 when the amplitude change of the input signal is large. If the current flowing through the constant voltage flll'9 is 12, and the capacitance of the hold capacitor 12 is C, then the output signal V
The rate of change in O is expressed as 12/C. This ■2 /
The larger the value of C, the better the ability to follow amplitude changes in the input signal Vi. However, the value of current I2 is
There is a limit due to the capacitance of transistors 6 and 7, and there is also a limit due to the desire not to increase power consumption, so it cannot be made too large. On the other hand, the capacitance C of the hold capacitor 12 cannot be made too small because if it is made small, the hold time will be limited, and input signals with a large period cannot be held accurately. Therefore, when the amplitude change of the input value @v1 is large, the output signal VO will look like the third @ dotted line if it is ideally held, but in reality it will look like the solid line in Figure 3, with the error dVo was occurring.

The present invention has been made to eliminate the drawbacks of the conventional circuits described above, and an object of the present invention is to provide a sample-and-hold circuit that has good followability for input signals with large amplitude changes.

The present invention is a sample and hold circuit that includes an emitter follower circuit that forcibly charges and discharges a hold capacitor when folded.

Embodiments of the present invention will be described below based on the drawings.

FIG. 4 is a circuit diagram 1j showing an embodiment of the present invention.

The base of the transistor 15 and the base of the transistor 16 are connected to the input terminal 1. transistor 1
The collector of No. 5 is grounded. The emitter of transistor 15 is connected to the collector of transistor 6 of transistor 6 and transistor 7 forming a differential amplifier similar to the conventional circuit described above. The collector of the transistor 16 is connected to the power supply terminal 14.

[The emitter of the transistor 16 is connected to the collector of the transistor 7. Similar to the conventional circuit described above,
A base bias power supply 8 is connected to the base of the transistor 6. A constant current source 9 is connected to the emitter of the transistor 6 and the emitter of the transistor 7.

The base of transistor 7 is connected to the sampling pulse input terminal. The emitter of transistor 15 and the collector of transistor 6 are connected to power supply terminal 14 via resistor 1117. The emitter of transistor 16 and the collector of transistor 7 are connected to power supply terminal 14 via a resistor. Further, the emitter of the transistor 15 is connected to the base of the transistor 19. The emitter of transistor 16 is also connected to the base of transistor 20 . The collector of transistor 19 is connected to power supply terminal 14 . The emitter of transistor 19 and the emitter of transistor 20 are connected at a connection I[S21. The collector of transistor 20 is grounded. A hold capacitor 12 is connected to the connection part 21 and the earth ground. The connecting portion 21 is connected to the output terminal 13. Transistors 15, 16, 19 and 20 each constitute an emitter follower and their voltage amplification factor is unity.

Next, the operation of the circuit shown in FIG. 4 will be explained.

The relationship between the level of the sampling pulse Vp and the level of the bias voltage V and the magnitude of the voltage Wi I 2 are the same as in the conventional circuit described above. The input signal v1 input to the input terminal 1 is applied to the base of the transistor 15 and the base of the transistor 16, and is applied to the base of the transistor 19 via the transistor 15. Here, first, the sampling pulse ■p is H″
Then, as described above, transistor 7 is turned on, so the emitter follower consisting of transistor 16 and transistor 7 works, and input tM is applied to the base of transistor 20 via transistor 16. It will be done. As described above, the input signal 1 is also applied to the base of the transistor 19, so that the transistor 19 and the transistor 20 are turned on, and the input signal Vi is supplied to the hold capacitor 12. At this time, if the potential of the output signal VO immediately before being sampled is higher than the potential of the input signal v1 at the time of sampling, the emitter follower of the transistor 20 is connected to the hold capacitor 12.
If the potential is lower than the potential of the input signal 1, the hold capacitor is charged by the emitter follower of the transistor 19. Here, the base currents of transistor 19 and transistor 20 are 1a and 1a, respectively.
9 and 162o, and the common emitter current amplification factors of transistor 19 and transistor 20 are h.

Jin, 9 and hF! 20, the charging current of the hold capacitor 12 is h"rt+9·I8.

Therefore, the discharge current of the hold capacitor 12 is hrc
2o-Iazo. Here, when compared with the conventional sample and hold circuit, the base current is 18.9 and IIA
Since 2G is the predistribution current I2, the charging and discharging currents of the hold capacitor 12 are hre+9·Iz and hFt20''■2, respectively.Here, as an example, the transistors 19 and 20 are connected to an IC (integrated Since hF is approximately 50'c'', the charging and discharging current of the hold capacitor 12 is 50I2, which is 50 times the charging and discharging current of the conventional sample and hold circuit. Therefore, the charging/discharging time during sampling can be significantly shortened, and the output signal vO also draws an ideal curve as shown by the dotted line in FIG.

As described above, according to the present invention, it is possible to obtain a sample-and-hold circuit that has good followability for input signals with large amplitude changes and can sample and hold the input signals with high accuracy. 'L

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional sample and hold circuit. FIG. 2 is a schematic diagram showing signal waveforms at each part of FIG. 1. Figure i@3 is a schematic diagram showing signal waveforms at various parts in Figure 1 when the amplitude change of the input signal is large. FIG. 4 is a circuit diagram showing an embodiment of the present invention. In the figure, 6, 7.15, 16. ．． 19. 20 is a transistor, 8 is a base bias power supply, 9 is a constant current source, 1
2 is a hold capacitor, and 17° and 18 are resistors. Representative: Shin Kuzuno - (1 other person)
￥1 figure '44 figure

Claims (1)

[Claims] First and second transistors whose input portions are connected to each other and into which an input signal to be sampled and held is input; the first and second input portions; and a second output section, the bias power supply is input to the first input section, the sampling signal is input to the second input section, and the first output section is connected to the first output section. Connected to the output part of the transistor. The second output section is a differential amplifier connected to the output section of the 182 transistors, the third transistor whose input section is connected to the output section of the first transistor, and the input section is connected to the output section of the first transistor. a fourth transistor connected to the output part of the second transistor, the output part of the third transistor and the output part of the fourth transistor are connected to each other, and the connection part and the fourth transistor are connected to each other. The third transistor further comprises a capacitor connected to the ground, the third transistor constitutes a charging circuit for the capacitor, the fourth transistor constitutes a discharging circuit for the capacitor, and one part of the abutment contact A sample and hold circuit that outputs a sampled and held output signal.