EP0667057A1

EP0667057A1 - Active impedance termination

Info

Publication number: EP0667057A1
Application number: EP94923969A
Authority: EP
Inventors: Stephen W. Hobrecht
Original assignee: National Semiconductor Corp
Current assignee: National Semiconductor Corp
Priority date: 1993-09-02
Filing date: 1994-07-15
Publication date: 1995-08-16
Also published as: KR950704855A; WO1995006977A1

Abstract

An active impedance termination circuit is composed of a differential amplifier stage composed of a long-tailed pair of transistors (12, 13) and a current mirror load (16, 17) which produces a single-ended output (18). A constant current supply (14) provides the tail current (IT) of the long-tailed pair and it can be varied in response to a control potential (15). The output (18) is connected to the inverting input (13) thereby producing 100 % negative feedback and unity voltage gain exists between the noninverting input and the output. A capacitor (20) is coupled to the inverting input and a bias potential applied to the noninverting input. The circuit acts to force the capacitor charge to equal the bias potential. This basic circuit can be configured to function as a high pass filter or a low pass filter.

Description

ACTIVE IMPEDANCE TERMINATION Background of the Invention

An integrated circuit (IC) is employed to control the charging and discharging of a small capacitor. In the prior art where a small value on chip capacitor is employed, a large value resistor must be employed to produce a reasonable R-C time constant. Alternatively, it has been known to employ a differen¬ tial amplifier (diff-amp) to produce a suitably low constant current charging and discharging action. Typically, the diff-amp takes up less chip area than an equivalent high value resistor. Furthermore, the charging current, being constant, produces a linear charge or discharge. Such circuits are commonly employed in oscillators where the diff-amp is switched between the charge and discharge states by suitable control circuitry.

Summary of the Invention

It is an object of the invention to provide an IC that will charge and discharge a small capacitor and the current provided is terminated when the capacitor potential equals a reference potential.

It is a further object of the invention to provide an IC that can charge and discharge a small on chip capacitor relative to a reference potential and the circuit current can be controlled to determine the charge and discharge rate.

It is a still further object of the invention to provide an IC that can charge and discharge a capacitor relative to a reference and to embody the circuit in low pass filter or a high pass filter, in which the circuit current control determines the critical frequencies. These and other objects are achieved in an IC which consists of a charge/discharge circuit composed of a diff-amp, con¬ figured as a long tailed pair, having its output connected to its inverting input. A small capacitor, suitable for an IC on chip location, is coupled to the inverting input and a reference poten¬ tial (V) coupled to the noninverting input. The diff-amp tail current is determined by a controllable constant current element. When the capacitor charge is below V, the circuit will charge the capacitor at a constant current until the charge equals V. When the capacitor charge is above V, the circuit will discharge the capacitor until the charge equals V. The charge and discharge are constant and the rate is determined by the diff-amp tail current. This circuit can be con figured with either bipolar or CMOS elements

The basic circuit can be the central part of typical dynamic circuits, such as a low pass filter or a high pass filter. The critical filter frequencies can be controlled by the capacitor value and varied by means of the tail current control.

Brief Description of the Drawing

Figure 1 is a schematic diagram of the bipolar transistor version of the circuit of the invention.

Figure 2 is a schematic diagram of the CMOS transistor version of the circuit of the invention.

Figure 3 is a schematic diagram of a low pass filter using the circuit of the invention.

Figure 4 is a schematic diagram of a high pass filter using the circuit of the invention. Description of the Ivention With reference to the schematic diagram of fi,gure 1, a V power supply is connected + to terminal 10 and - to ground terminal 11. Transistors 12 and 13 comprise a differential pair, configured as a long tailed pair, and the tail current (I„) is supplied by constant current element 14. The value of I„ is determined by the bias potential applied to control terminal 15. The base of transistor 12 is the non¬ inverting input and the base of transistor 13 is the inverting input. Diode connected transistor 16 and transistor 17 are connected as a current mirror load and are connected respec¬ tively to the collectors transistors 12 anc¹ 13. The collector of transistor 17 provides the circuit outp-.- at terminal 18.

The output of the circuit at terminal 18 is con¬ nected to the inverting input, at the base of transistor 13, so that the circuit incorporates 100% negative feedback. This means that the circuit will function as a unity gain voltage follower. A voltage source 19 (V), having a value below V , is connected to the base of transistor 12 and the stage will act to drive the output at terminal 18, to the level of V.

Capacitor 20 is desirably an on chip device which has a relatively small value (typically less than about 50 pf). If the initial charge on capacitor 20 is less than V (for example, when the circuit is first energized, the charge will be zero) , the circuit will cause I_τ to flow in transistor 13, thereby to charge capacitor 20. The charge will be constant because the current is constant. During this action, transistor 12 and, consequently, transistors 16 and 17 will be off. If capacitor 20 has an initial charge in excess of V (for example, the charge on capacitor can be equal to V under some conditions), transistor 13 will be turned off and I_, flows in transistor 12. This means that I_, will flow in transistors 16 and 17. If they are matched, I_, will be sunk out of capacitor 20 so that it will discharge linearly. The circuit will act to force the capacitor charge to the level of V at which point it will be balanced and I„ will be split equally in tran- sisors 12 and 13. Thus, I_τ/2 will flow in transistors 13 and 17 so that capacitor 20 will have its charge clamped at V.

Figure 2 is a schematic diagram of a CMOS version of the circuit of figure 1. The PNP transistors have been replaced by P channel MOSFETs and the NPN transistors replaced with N channel MOSFETs. The CMOS transistors numerals include a prime sign and where the circuit elements are the same as those of figure 1, the same numerals are used. By way of explanation, the CMOS sources function in the same way as the BJT emitters, the drains function as collectors, and the gates function as bases. About the only significant difference is that the CMOS version of figure 2 will not have base-current errors that are always present in the bipolar figure 1 circuit and the voltage follower action will be somewhat more accurate.

Figure 3 is a schematic diagram wherein the diff- amp circuit of figure 1 is used to form a high pass filter. Capacitor 20, instead of being grounded, is returned to input terminal 21 and an a-c input signal 22 is applied thereto. It is to be understood that the peak voltage of input 22 is smaller than V. At low frequencies the circuit will charge and discharge capacitor 20 so that the potential at the base of transistor 13 is held constant at V. Thus, the signal output is zero. However, a high frequencies, the charge and discharge of capacitor 20 can¬ not occur rapidly enough to follow and, in effect, the signal from 22 will be coupled to the output terminal 18. Thus, at high frequencies the circuit will display unity gain between terminals 21 and 18. Clearly, the knee of the transfer function will be determined by the value of I_τ, the capacitor value, and the voltage amplitude. Thus, the bias applied to terminal 15 can control the frequency at which the knee occurs.

Figure 4 is a schematic diagram wherein the circuit of figure 1 is used to form a low-pass filter. Here the a-c signal input source 22 is coupled in series with bias source 19. While source 22 is shown coupled between source 19 and terminal 23, it can function the same if it is located on the ground side of source 19. At low frequencies, as the voltage at terminal 23 varies, capacitor 20 can charge and discharge due to the unity gain stage action and terminal 18 will follow. However, at the higher frequencies, capacitor 20 cannot charge and discharge rapidly enough to follow. At some high frequency the charge and discharge is so slow that substantially zero signal will occur at terminal 18. The knee of the low-pass filter response will thus be a function of I_τ, the capacitor value, the voltage amplitude, and will be determined by the bias at terminal 15.

While figures 3 and 4 are shown based upon figure 1, it is clear that in each case the circuit of figure 2 could be used. Which form is employed will be a choice available to the circuit designer. That choice will be determined largely by the kind of circuits employed elsewhere on the IC chip.

The invention has been described and a preferred embodiment detailed. Alternatives have also been described. When a person skilled in the art reads the foregoing description, other alternatives and equivalents, within the spirit and intent of the invention, will be apparent. Accordingly, it is intended that the scope of the invention be limited only by the claims that follow.

Claims

I claim:

1. An active impedance termination circuit com¬ prising: a pair of transistors connected together to function differentially as a long-tailed pair and having inverting and noninverting inputs; a constant current source coupled to supply the tail current in said long-tailed pair; a current mirror load connected to said long- tailed pair to provide a single-ended output; a capacitor coupled to said inverting input; means for coupling said single-ended output to said inverting input thereby providing 100% negative feedback and producing unity voltage gain between said noninverting input and said output; and a source of bias potential coupled to said noninverting input whereby said circuit acts to force the charge on said capacitor to match said bias potential.

2. The active impedance termination circuit of claim 1 wherein said constant tail current magnitude is varied as a function of a control potential whereby the charge or dis¬ charge rate of said capacitor can be varied by means of said control potential.

3. The active impedance termination circuit of claim 2 wherein said transistors are bipolar junction transistors.

4. The active impedance termination circuit of claim 2 wherein said transistors are monopolar CMOS transistors.

5. The active impedance termination circuit of claim 2 further including a source of signal applied in series with said capacitor whereby a high pass filter action is achieved at said output terminal.

5. The active impedance termination circuit of claim 2 further including a source of signal applied in series with said source of bias potential and a low pass filter action is achieved at said output terminal.