JPH02690Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in peak hold circuits used, for example, in integrated circuits for level meters.

Generally, in order to hold the peak voltage of an AC signal, the capacitor is charged quickly during a predetermined half-wave period of the AC signal, the capacitor is quickly charged during the remaining half-wave period, and the capacitor is gradually charged during the remaining half-wave period. It is necessary to discharge the battery. Usually, it is charged by the output of an emitter follower circuit and discharged by a high resistance or low constant current source.

FIG. 1 shows a conventional peak hold circuit, in which 11 is a first power supply terminal, 12 is a second power supply terminal (grounded in this example), 13 is an AC signal input terminal, 14 is a bias generation circuit, Q ₁ and Q ₂ are the first and second differential pairs in which each emitter is common.
transistor Q ₉ is a constant current source transistor for a differential circuit, 16 is a current mirror circuit consisting of third and fourth transistors Q ₃ and Q ₄ ;
7 is an input capacitor connected between one input terminal of the differential circuit (the base of the first transistor Q ₁ ) and the input terminal 13; Q ₅ is a transistor that amplifies one output of the differential circuit; _Q6 is a current source transistor connected to the collector of this transistor _Q5 , _Q7 is an emitter follower transistor whose input is the output of the transistor _Q5 , and 18 is the output terminal of this emitter follower transistor _Q7 . A hold capacitor 19 is connected between the ground terminal and the hold output terminal for deriving the hold output of this capacitor 18. _Q8 is a hold capacitor connected between the emitter of the emitter follower transistor _Q7 and the ground terminal. This is a low constant current source transistor inserted, and the output terminal 19 is DC-connected to the other input terminal (base of the second transistor _Q2 ) of the differential circuit. Note that R ₁ to R ₄ are resistances.

In the above peak hold circuit, during the positive half cycle of AC input, transistor Q ₁ is turned on, so rectification is performed, and a current corresponding to the input signal level flows through the subsequent transistors Q ₅ and Q ₇ , and the capacitor 18 is rapidly charged, and a charging voltage corresponding to the input signal level is obtained. During this time, transistor _Q2 is turned off. In the next negative half cycle, transistor Q ₂ , which is biased by the charge charged in the capacitor 18, is turned on, transistors Q ₁ and Q ₅ are turned off, and transistor
_Q7 turns off because the base potential becomes lower than the emitter potential. During this time, the charge in the capacitor 18 is gradually discharged through the low constant current source transistor _Q8 . Note that without this low constant current source transistor _Q8 , the discharge path of the capacitor 18 would be only the base current of the transistor _Q2 ,
This value is usually very small, and considering variations in h _FE (current amplification factor) during the integrated circuit manufacturing process, a constant amount of discharge cannot be expected.

Through such charging and discharging operations, the peak value of the rectified half-wave period of the AC signal input is held in the capacitor 18.

However, the peak hold circuit shown in FIG. 1 as described above has a drawback in that it uses a large number of elements.

The present invention was developed to eliminate the above-mentioned drawbacks, and one of the differential pair transistors connected to the hold capacitor is saturated during the non-rectified half-wave period of the AC signal input, so that a certain amount of electricity is supplied from the capacitor. The present invention provides a peak hold circuit in which the number of elements used can be reduced by having a circuit configuration that allows discharge to occur.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. Compared to the peak hold circuit shown in FIG. 1, the peak hold circuit shown in FIG. 2 connects the base and collector of the third transistor Q ₃ of the current mirror circuit 21 to each other, _and The output of _the second transistor Q ₂ of the differential pair transistors Q ₁ and Q ₂ is input directly to the base of the emitter follower transistor Q ₇ , and The difference is that the amplification transistor Q ₅ , current source transistors Q ₆ , Q ₈ , and resistors R ₃ and R ₄ are omitted, but the rest is the same, so the same parts in Fig. 2 as in Fig. 1 are given the same reference numerals. Therefore, the explanation will be omitted.

In the peak hold circuit shown in Figure 2, in the positive half cycle of AC signal input, transistor Q ₁
is turned on, rectification is performed, and at this time, a current according to the input signal level flows through the transistor _Q3 of the current mirror circuit 21, and a current equal to this current flows from the transistor _Q4 to the emitter follower transistor _Q7 . flows to the base, this transistor
The capacitor 18 is rapidly charged by _Q7 , and a charging voltage corresponding to the input signal level is obtained. During this time, transistor _Q2 is turned off.

In the next negative half cycle, the capacitor 18
A transistor biased with a charging charge of
Q ₂ is on, transistor Q ₁ is off, and each transistor Q ₃ and Q ₄ of the current mirror circuit 21 is off, so the emitter follower transistor
Q ₇ is also turned off. During this time, the above transistor _Q2
Since no collector current is supplied to the capacitor 18, the charge in the capacitor 18 is discharged between the base and emitter of the transistor _Q2 and through the constant current source transistor _Q9 . That is, at this time, the transistor _Q2 is saturated and a certain amount of discharge is possible. Due to this charging/discharging operation,
The peak value of the rectified half-wave period of the AC signal input is held in the capacitor 18.

FIG. 3 shows another embodiment, in which the signal input terminal 13 is connected to the base of the transistor Q ₂ via the input capacitor 17 and the resistor R ₅ , and the output terminal 19 is This has been changed so that it is connected to the base through the resistor _R6 , and the rest is the same, so the same parts in FIG. 3 as in FIG.

In the peak hold circuit shown in Fig. 3, the second
The circuit operates in accordance with the circuit shown in the figure, and in the negative half cycle of AC input, transistor Q ₂ is turned off, transistors Q ₁ , Q ₃ , Q ₄ , and Q ₇ are turned on, and capacitor 18 is charged. , in the positive half cycle the base potential of transistor Q ₂ is [capacitor 1
8 charging voltage + AC signal input], but the base of transistor Q ₁ is fixed (bias voltage 2V _BE from bias circuit 14, where V _BE is the voltage between the base and emitter of the transistor), so transistor Q ₁ is off, Therefore, transistors Q ₃ , Q ₄ ,
While Q ₇ is also off, transistor Q ₂ is on, and its collector current is not supplied, so that the base-emitter voltage of transistor Q ₂ is saturated and the charge in capacitor 18 is discharged.

As described above, according to the peak hold circuit of the present invention, one of the differential pair transistors connected to the hold capacitor is saturated during the non-rectified half-wave period of the AC signal input, and a certain amount of electricity is output from the capacitor. Since the circuit is configured to cause discharge, it is possible to omit the current source required for discharge in conventional peak hold circuits, which reduces the number of elements used and reduces costs. There is.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional peak hold circuit, FIG. 2 is a circuit diagram showing an embodiment of the peak hold circuit according to the present invention, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. be. Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₇ , Q ₉ ...transistor,
11, 12...power supply terminal, 14...bias generation circuit, 18...capacitor, 21...current mirror circuit.

Claims (1)

[Claims for Utility Model Registration] First and second transistors whose emitters are commonly connected and form a differential pair, and which are inserted between the collector of the first transistor and the first power supply terminal, and whose base and collector are mutually connected. and a fourth transistor inserted between the collector of the second transistor and the first power supply terminal, and whose base is connected to the base of the third transistor. a constant current source inserted between the common emitter of the first and second transistors and a second power supply terminal; a bias generation circuit that supplies a bias voltage to the base of the first transistor; an emitter follower transistor whose base is connected to a potential corresponding to a connection point between the second transistor and the fourth transistor and whose emitter is DC-connected to the base of the second transistor; and an emitter follower transistor of the emitter follower transistor. and a second power supply terminal; and a circuit for applying an AC signal input to the base of either the first or second transistor. circuit.