JPH0113480Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a clamp circuit that keeps the DC level of a video signal constant.

As shown in Fig. 1, this type of conventional
A capacitor 13, a diode 20, and a bias reference power supply 1 are connected between the input terminal 11 and the output terminal 12.
7 and a resistor 18 are connected. In this circuit, when there is no signal at the input terminal 11, the voltage at the output terminal 12 is the difference between the voltage V _B of the reference power supply 17 and the forward drop voltage V _F of the diode 20, that is, V _B
-V _F , and if the voltage at the output terminal 12 drops below V _B -V _F for some reason, a charging current flows from the reference power supply 17 to the capacitor 13 through the diode 20, and the voltage at the output terminal 12 decreases to V _B - When V _F is reached, charging ends, and if for some reason the voltage at the output terminal 12 rises above V _B - _{V F} , a discharge current flows from the capacitor 13 through the resistor 18, and the voltage at the output terminal 12 increases to V _B When -V _F is reached, the discharge ends, and as a result, the voltage at the output terminal 12 is always kept constant. When the video signal shown in FIG. 2 is applied to the input terminal 11, the capacitor 13 is charged at the lowest voltage portion of the synchronization section a, so the voltage at the output terminal 12 is clamped to a constant voltage. At point b, the capacitor 13 is discharged, but if the time constant determined by the capacitance of the capacitor 13 and the resistance value of the resistor 18 is made sufficiently longer than the period of the line frequency of the video signal, the voltage change in the video section b due to the discharge of the capacitor 13 can be suppressed. It can be suppressed to a very small amount.

However, in order to clamp the synchronizing part a as quickly as possible, it is preferable that the capacitance of the capacitor 13 is small so that the charging current of the capacitor 13 is small. As the voltage change becomes large, the waveform at the output terminal 12 becomes sloping (sag) at the pedestal as shown in FIG.
If the capacitance of 3 is increased, a large amount of current is required to charge it, and the synchronous part a cannot be clamped quickly, so good clamping characteristics cannot be obtained in any case. It was hot.

The object of this invention is to eliminate the drawbacks of the above-mentioned conventional circuits and to provide a clamp circuit that provides good clamping characteristics.

This invention will be explained with reference to embodiments shown in the drawings.

FIG. 4 shows an embodiment of this invention, where 1 is an input terminal, 2 is an output terminal, 3 is a capacitor, 4, 5,
6 is a transistor, 7 is a reference power supply for bias,
8 is a resistor for discharging, and 9 is a resistor for preventing distortion of the video signal when the transistor 5 is conductive.

In this clamp circuit, when there is no signal at the input terminal 1, the base voltage of the transistor 5 is the sum of the voltage V _B of the reference power supply 7 and the base-emitter forward voltage V _BE5 of the transistor 5, that is, V _B + V _BE5.
, and the base voltage of transistor 4 is the sum of the base voltage of transistor 5 V _B +V _BE5 and the base-emitter forward voltage V _BE4 of transistor 4,
That is, V _B +V _BE5 +V _BE4 , and this voltage is charged to the capacitor 3 and balanced. If the base voltage of transistor 4 decreases for some reason,
Since the base voltage of transistor 5 also decreases, its collector voltage increases, and this voltage is returned to the base of transistor 4 via transistor 6, so that the base voltage of transistor 4 becomes V _B +V _BE5 +
When it reaches V _BE4 , it is balanced, and if the base voltage of transistor 4 increases for some reason, the base voltage of transistor 5 also increases, so its collector voltage decreases, and this voltage is applied to the base of transistor 4 via transistor 6. When the voltage is fed back and the base voltage of transistor 4 reaches V _B +V _BE5 +V _BE4 , it is balanced, and as a result, the base voltage of transistor 4, and therefore its emitter voltage, that is, the voltage at output terminal 2, is always kept constant. . When the video signal shown in FIG. 2 is input to the input terminal 1, the feedback occurs so that the base voltage of the transistor 4 becomes V _B +V _BE5 +V _BE4 at the lowest voltage part of the synchronizing part a. is charged, so the voltage at output terminal 2 is clamped to a constant voltage,
On the other hand, in video section b, capacitor 3 discharges through resistor 8, but the capacitance of capacitor 3 is compared so that the time constant determined by the capacitance of capacitor 3 and the resistance value of resistor 8 is sufficiently longer than the period of the line frequency of the video signal. Since the target is set large, capacitor 3
The voltage change in the image section b due to the discharge of is suppressed to a very small amount. Even if the capacitor 3 has a relatively large capacity, the voltage change in the synchronous part a is amplified by the transistor 5, and the current is amplified by the transistor 6, and then the capacitor 3 is charged. Therefore, the capacitor 3 is charged quickly. Therefore, good clamping characteristics can be obtained.

Since this invention is constructed as described above, even if the capacitance of the capacitor is set to be relatively large, the capacitor can be quickly charged, and therefore, good clamping characteristics can be obtained. It is effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional device, FIGS. 2 and 3 are waveform diagrams, and FIG. 4 is a circuit diagram showing an embodiment of this invention. 1, 11: input terminal, 2, 12: output terminal,
3, 13: Capacitor, 4, 5, 6: Transistor, 7, 17: Reference power supply, 8, 18: Resistor, 9:
Resistor, 20: diode.

Claims (1)

[Scope of utility model registration request] connecting the base of a second transistor whose emitter is connected to a reference power source to the emitter of the first transistor whose base is connected to the input terminal via a capacitor and whose emitter is connected to the output terminal;
A clamp circuit in which a third transistor forming an emitter follower is connected to the collector of the second transistor and the base of the first transistor.