JPS6122291Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a peak hold circuit, and in particular,
The present invention relates to a peak hold circuit that has excellent linearity and can provide an output that matches the input signal level.

A peak hold circuit receives an input signal and holds it at a constant value, and is used in various signal processing circuits.

FIG. 1 shows such a peak hold circuit, and numeral 1 denotes a differential amplifier to which a signal is applied to its positive input terminal, and whose output terminal is directly connected to its negative input terminal. 1a is a signal input terminal. 2 is a diode, 3 is a capacitor, 4 is a resistor, and 5 is an output terminal.

When a signal V ₁ with a voltage waveform as shown in FIG _. becomes V ₂ =V ₁ . When such a signal V ₁ is input, charge is accumulated in the capacitor 3 via the diode 2 . At this time, the voltage on the cathode side of diode 2, that is, the voltage at output terminal 5
V ₃ becomes lower than the anode side voltage V ₂ (therefore, the input signal voltage V ₁ ) by the forward voltage drop of the diode 2. During the period _T1 in which the input signal voltage _V1 is below the peak value _V11 , the charge accumulated in the capacitor 3 is released with a time constant determined by the resistance value of the parallel resistor 4, but if this time constant is large enough, the output terminal The voltage of V 5 is almost constant V ₀₁ (=V ₁₁ −V _D , V _D : voltage drop across diode 2), and remains at this level until the next period T ₂ when a signal at a level equal to or higher than the peak value V ₁₁ is input.
V ₀₁ is retained. (Figure _2b ) During period T2, a signal with a peak value of _V12 is input, so diode 2 is connected from the output side of differential amplifier 1.
Current is supplied to the capacitor 3 via the capacitor 3, and the charge is accumulated in the capacitor 3, so the output terminal 5
The voltage increases and remains constant at a constant value V ₀₂ in the same way as before.
(=V ₁₂ −V _D ) is maintained. (Figure 2b) In this way, the output level corresponding to the peak value of the input signal is maintained, but the output signal voltage is lower than the input signal voltage by the forward voltage drop of diode 2. .

In order to improve this point, as shown in Figure 3,
A series circuit of a diode 7 and a resistor 8 is inserted between the output terminal of the differential amplifier 1 and the power supply 6, and the differential amplifier 1
the negative input terminal of , and the diode 7 of this series circuit.
and connection A of resistor 8 are directly connected.

9 is a current adjustment resistor.

Since the voltage V A at the connection point _A is equal to the input signal voltage V ₁ , the anode side voltage of the diode 7 becomes V ₁ +V _D. Therefore, the voltage on the cathode side of the diode 2, that is, the voltage at the output terminal 5 becomes _V1 . However, it is necessary to cause the output signal level to follow changes in the input signal level. That is, the output signal level V ₀ is V ₀ = kV ₁
It needs to be expressed as (k: constant), and the value of low resistance for this linearity adjustment is set.

However, if the value of the resistor is set to perform such linearity adjustment, the impedance conditions will change, and as mentioned above, the input signal level V ₁ and the output signal level V ₀ will not match, and accurate peak hold will not be performed. There were flaws.

The present invention has been made in consideration of the above points, and aims to provide a peak hold circuit which is excellent in linearity and can obtain an output level that coincides with the peak value of an input signal, and which comprises a differential amplifier, a first diode connected in a forward direction to the output terminal of the differential amplifier, a parallel circuit of a capacitor and a resistor provided between the cathode terminal of the first diode and ground, and a second diode connected between the connection point of the differential amplifier and the first diode and the output terminal of a DC power supply.
a linearity adjustment circuit in which two resistors are connected in series, and a second diode connected in reverse between the resistor connection point of the series circuit and the output terminal of the differential amplifier, the negative input terminal of the differential amplifier is connected to the resistor connection point of the linearity adjustment circuit, and an input signal to be peak-held is applied to the positive input terminal of the differential amplifier, wherein an amplifier for amplifying a signal appearing at the cathode terminal of the first diode is provided on the cathode side of the first diode, and a peak hold signal is obtained from the output terminal of the amplifier.

FIG. 4 is a configuration diagram of one embodiment of the present invention, and the same parts as in FIG. 3 are given the same reference numerals.

In FIG. 4, 10 is an amplifier, and the input terminal of this amplifier 10 is connected to the cathode side of the diode 2. The amplification degree of this amplifier 10 is 1/k
is set to .

In this circuit, as described in connection with FIG. 3, linearity adjustment is performed by the resistors 8 and 9, and the input signal level applied to the input terminal 1a is
The signal level V ₁ applied to the input terminal of the amplifier 10 with respect to V ¹ is expressed as V ¹ =kV ₁ . When this signal is amplified by 1/k times the input to the amplifier 10, the amplifier 10
The output V ₄ of is V ₄ =1/k(kV ₁ )=V ₁ , and the output signal level V ₄ matches the input signal level V ₁ applied to the input terminal 1a.

As is clear from the above description, the peak hold circuit according to the present invention not only has excellent linearity but also has the advantage of outputting a signal that matches the level of the input signal and performing accurate signal processing.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional peak hold circuit.
FIG. 2 is an explanatory diagram of the operation of the peak hold circuit shown in FIG. 1, FIG. 3 is a block diagram of a conventional peak hold circuit, and FIG. 4 is a block diagram of an embodiment of the present invention. 1: differential amplifier, 2: diode, 3: capacitor, 4: resistor, 5: output terminal, 7: diode, 8, 9: resistor, 10: amplifier.

Claims (1)

[Scope of utility model registration request] a differential amplifier; a first diode forwardly connected to the output terminal of the differential amplifier; a parallel circuit of a capacitor and a resistor provided between the cathode terminal of the first diode and ground; a linearity adjustment circuit in which two resistors are connected in series between a connection point between an amplifier and the first diode and an output terminal of a DC power supply; a connection point between the resistors of the series circuit; and an output of the differential amplifier. a second diode connected in the opposite direction between the terminals, a negative input terminal of the differential amplifier is connected to a resistance connection point of the linearity adjustment circuit, and a second diode is connected to the positive input terminal of the differential amplifier. In a peak hold circuit configured to apply an input signal to be peak held, an amplifier is provided on the cathode side of the first diode to amplify a signal appearing at the cathode terminal of the first diode, and the peak hold is applied from the output terminal of the amplifier. A peak hold circuit characterized in that a hold signal is obtained.