JPH01265718A - Schmitt trigger circuit - Google Patents
Schmitt trigger circuitInfo
- Publication number
- JPH01265718A JPH01265718A JP63095009A JP9500988A JPH01265718A JP H01265718 A JPH01265718 A JP H01265718A JP 63095009 A JP63095009 A JP 63095009A JP 9500988 A JP9500988 A JP 9500988A JP H01265718 A JPH01265718 A JP H01265718A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- input signal
- circuit
- threshold
- threshold voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 23
- 230000007257 malfunction Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 9
- 238000006085 Schmidt reaction Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
- H03K3/2893—Bistables with hysteresis, e.g. Schmitt trigger
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
- H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manipulation Of Pulses (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は、入力信号電圧の変動に対する誤動作防止を
図るようにしたシュミツ１〜１〜リガ回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a Schmidts 1-1-Riga circuit designed to prevent malfunctions due to fluctuations in input signal voltage.
（従来の技術）
一般に、シュミツト１〜リガ回路はアナログ回路とディ
ジタル回路との間のインターフェースに使用される。す
なわち、シュミットトリガ回路は、回路特有のヒステリ
シス電圧を利用して、緩慢に変化するアナログ電圧を急
峻に変化するディジタル波形に変換する。これにより、
アナログ電圧が持つ雑音と寄生発振信号等が除去される
。このような変換を行なうため、シュミット１へリカ回
路は高レベルと低レベルの２種類の閾値電圧との間にヒ
ステリシス特性を持たせて設計される。従って、シュミ
ットトリガ回路を設計する上で重要な条件は、２種類の
閾値電圧とヒステリシス電圧とを要求される値に設層す
ると同時にそれぞれの再現竹が良いことである。(Prior Art) Generally, Schmidt 1 to Rigger circuits are used as an interface between analog circuits and digital circuits. That is, the Schmitt trigger circuit converts a slowly changing analog voltage into a rapidly changing digital waveform by using a hysteresis voltage unique to the circuit. This results in
Noise and parasitic oscillation signals of analog voltages are removed. In order to perform such conversion, the Schmitt 1 helical circuit is designed to have hysteresis characteristics between two types of threshold voltages, high level and low level. Therefore, an important condition in designing a Schmitt trigger circuit is to set the two types of threshold voltages and hysteresis voltage to the required values, and at the same time, to ensure good reproduction of each.
第１図（マ従来のシュミツ１−１〜リガ回路の一例を示
す回路図である。図において、７１は入力信号ｖｉｎを
バイアスづる直流電圧源、７２．７３はそれぞれ上記入
力信号ｖｉｎを高レベル側の一定の閾値電圧ＶＡもしく
は低レベル側の一定の閾値電圧ＶＣと比較する演算増幅
器、１４は電源電圧Ｖ。０とアースとの間に複数個の抵
抗が直列接続されて構成され、上記２種類の閾値電圧Ｖ
Ａ及びＶＣを発生でる電圧分割回路、７５は上記両演算
増幅器７２．７３の各出力がセラ１へ入力Ｓ及びリセッ
ト人力Ｒして供給されるセラ１−・リセツ］〜型のＲＳ
Ｓフリップフロラ回路である。FIG. 1 is a circuit diagram showing an example of a conventional Schmidts 1-1 to Riga circuit. In the figure, 71 is a DC voltage source that biases the input signal vin, and 72 and 73 are the circuit diagrams that respectively bias the input signal vin to a high level. 14 is a power supply voltage V. It is composed of a plurality of resistors connected in series between 0 and ground, and Type of threshold voltage V
A voltage dividing circuit 75 generates A and VC, and 75 is a cellar 1-/reset type RS in which the respective outputs of the operational amplifiers 72 and 73 are supplied to the cellar 1 as an input S and a reset manual power R.
This is an S-flip Flora circuit.
このような回路において、入力信号ｖｉｎとして第８図
のタイミングチャー１−に示ずような信号を供給した場
合に、一方の演牌増幅器７２は入力信号ｖｉｎの電圧値
が高レベル側の閾値電圧ＶＡよりも高くなったとぎに゛
１″レベルの信号を出力し、それ以外のとぎは″○″レ
ベルの信号を出力する他方の演締増幅器７３は入力信号
７曲の電圧値がイバレベル側の閾値Ｎ斤ＶＣよりも低く
なったときに” １ ”しｌ＼ルの信号を出力し、それ
以外のとぎはパＯ“レベルの信号を出力する。従って、
フリップフロップ回路７５に供給されるセラｉ・信号Ｓ
及びリセット信号Ｒは第８図に示すように変化する。In such a circuit, when a signal as shown in timing chart 1- in FIG. 8 is supplied as the input signal vin, one of the rendition amplifiers 72 has a threshold voltage at which the voltage value of the input signal vin is on the high level side. The other performance amplifier 73 outputs a signal at the level "1" when it becomes higher than VA, and outputs a signal at the "○" level at other times. When it becomes lower than the threshold value N VC, a signal of "1" level is outputted, and at other times, a signal of level "0" is outputted. Therefore,
Sera i signal S supplied to flip-flop circuit 75
and the reset signal R changes as shown in FIG.
これらの信号によってフリップフロップ回路７５がセラ
］・もしくはりセットされ、入力信号ｖｉｎがディジタ
ル信号５Ｏ（１℃に変換されてフリップフロップ回路７
５から出力される。These signals set the flip-flop circuit 75 to zero, and the input signal vin is converted to a digital signal 5O (1°C) and output to the flip-flop circuit 75.
Output from 5.
ところで、上記従来のシコミット１〜リガ回路において
、入力信号ｖ１１）としてＶＴＲのコン１〜Ｄ−ルバル
ス信号の再生出力信号を供給する場合について考えてみ
る。ＶＴＲにおけるコントロールパルス信号は、磁気テ
ープに記録する時の記録電流、テープの走行速度、テー
プ自体の特性の違い等により、再生出力信号のレベルが
変！ＩＪ ｉる。また、その再生出力信号には機械的な
雑音にＪ：るノイズ、電源回路からの奇生発振信号やリ
ップル成分、電気回路にＪ５ける直流成分の変動、等が
重畳されている。従って、従来てはこのような点を考慮
して上記２種類の閾値電圧ＶＡ及びｖＣのレベルを設定
する必要がある。しかし、第９図のタイミングチャー１
−に示すように、コン［〜ロールパルス信号自体の再生
レベルどノイズの信号レベルが共に大きく、これに対し
て上記雨間１直電圧Ｖ△及びＶＣのレベルが低く設定さ
れているときには、実際にパルスのない期間にセラ１〜
信号Ｓもしくはリセット信号Ｒが演粋増幅器７２．７３
から誤って出力され、変換されたディジタル信号３ｏｕ
ｔには誤判別波形が生じる。他方、第１０図のタイミン
グチャートに示ずＪ：うに、コン１〜ロールパルス信号
自体の再生レベルとノイズの信号レベルが共に小ざく、
セット信号Ｓ及びリセット信号Ｒが全く発生ゼず、この
場合にもディジタル信号３’ｏｕ’ｔに誤判別波形が生
じる。By the way, let us consider the case where, in the conventional SICOMIT 1 to RIGA circuit, a reproduced output signal of the CON 1 to D-REV signals of a VTR is supplied as the input signal v11). The level of the playback output signal of the control pulse signal in a VTR varies depending on the recording current when recording on the magnetic tape, the running speed of the tape, the characteristics of the tape itself, etc. IJ iru. In addition, the reproduced output signal is superimposed with mechanical noise, a random oscillation signal and ripple component from the power supply circuit, fluctuations in the DC component in the electric circuit, and the like. Therefore, conventionally, it is necessary to set the levels of the two types of threshold voltages VA and vC in consideration of such points. However, timing chart 1 in Figure 9
- As shown in , when the reproduction level of the control pulse signal itself and the signal level of the noise are both high, and the levels of the above-mentioned direct voltage V△ and VC are set low, the actual Sera 1~ during the period with no pulse.
The signal S or the reset signal R is the arithmetic amplifier 72.73
The digital signal 3ou that was erroneously output and converted from
An erroneous discrimination waveform occurs at t. On the other hand, as shown in the timing chart of FIG. 10, the reproduction level of the control 1~roll pulse signal itself and the signal level of the noise are both small.
The set signal S and reset signal R are not generated at all, and an erroneous discrimination waveform occurs in the digital signal 3'out' in this case as well.
このように従来では、誤判別波形の出力が生じないよう
に２種類の閾値電圧レベルを設定する必要があるが、そ
の設定は非常に困難である。As described above, conventionally, it is necessary to set two types of threshold voltage levels so as not to output an erroneously determined waveform, but this setting is extremely difficult.
（発明−が解決しようとする課題）
このように従来のシュミツｊ〜１〜リカ回路では閾値電
圧の設定が困禦であり、入ツク信号の電圧が変動すると
誤動作するという問題がある。(Problems to be Solved by the Invention) As described above, in the conventional Schmidts circuit, it is difficult to set the threshold voltage, and there is a problem that it malfunctions when the voltage of the input signal fluctuates.
この発明は上記のような事情を考慮してなされたもので
あり、その目的は、閾値電圧の設定が不要であり、かつ
入力信号の電圧が変動しても誤動作を起こずことのない
シュミツ［ヘトリガ回路を提供することにある。This invention was made in consideration of the above circumstances, and its purpose is to create a Schmidts [ An object of the present invention is to provide a hetrigger circuit.
［発明の構成１
（課題を解決するための手段）
この発明のシュミツ１〜トリ力回路は、入力信号の最大
型Ｈを検、」」シ、保持する最大電圧検出手段と、人力
信号の最小電圧を検出し、保持する最小電圧検出手段と
、直列接続された３個以上の抵抗からなり、上記最大電
圧が一端に供給され、上記最小電圧値が他端に供給され
、これら□各抵抗の直列接続点から高レベル側の閾値電
圧並びに低レベル側の閾値電圧を発生ずる閾値電圧発生
手段と、上記入力信号の電圧と上記高レベル側の閾値電
圧とを比較する第１の電圧比較手段と、上記入力信号の
電圧と上記低レベル側の閾値電圧とを比較する第２の電
圧比較手段と、上記第１及び第２の電圧比較手段の出力
に基づいて制御されるフリップフロン１回路とを具備し
たことをＶｆＩ９２とする。[Structure 1 of the Invention (Means for Solving the Problems) The Schmidts 1 to Tri-power circuit of the present invention includes a maximum voltage detection means for detecting and holding the maximum type H of the input signal, and a maximum voltage detection means for detecting and holding the maximum type H of the input signal, and It consists of a minimum voltage detection means that detects and holds the voltage, and three or more resistors connected in series.The maximum voltage is supplied to one end, the minimum voltage value is supplied to the other end, and the voltage of each resistor is threshold voltage generating means for generating a high level side threshold voltage and a low level side threshold voltage from the series connection point; and first voltage comparing means for comparing the voltage of the input signal and the above high level side threshold voltage. , a second voltage comparison means for comparing the voltage of the input signal with the low-level threshold voltage, and a flip-flop circuit controlled based on the outputs of the first and second voltage comparison means. This is called VfI92.
（作用）
この発明のシュミットトリが回路では、入力信号の最大
電圧と最小電圧とが検出され、これら２種類の電圧を抵
抗結合することによって高レベル側及び低レベル側の閾
値電圧が形成される。このため、高レベル側及び低レベ
ル側の閾値電圧が入力信号の電圧変動に追随して変化し
、両開値電圧が常に最適な値に制御される。(Operation) In the Schmidt-Tori circuit of the present invention, the maximum voltage and minimum voltage of the input signal are detected, and threshold voltages on the high level side and low level side are formed by resistively coupling these two types of voltages. . Therefore, the threshold voltages on the high level side and the low level side change following the voltage fluctuation of the input signal, and both open value voltages are always controlled to the optimum value.
（実施例）
以下、図面を参照してこの発明を実施例により説明する
。 。(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings. .
第１図はこの発明に係るシュミツｌ−１−リガ回路を、
ＶＴＲのコントロールパルス信号の再生出力信号をディ
ジタル変換するための回路に実施した場合の構成を示す
回路図である。直流電圧源１１は、ＶＴＲのコントロー
ルパルス信号の再生出力信号である入力信号ｉ ｎを電
圧ｖＢにバイアスするためのものである。この電圧ｖ［
３でバイアスされた入力信号ｖｉｎは最大電圧検出回路
１２及び最小Ｎ圧検出回路１３に供給されると共に、そ
れぞれコンパレータを構成する演算増幅器１４の非反転
入力端子及び演算増幅器１５の反転入力端子に供給され
る。FIG. 1 shows a Schmidts l-1-Riga circuit according to the present invention.
FIG. 2 is a circuit diagram showing a configuration when implemented in a circuit for digitally converting a reproduced output signal of a control pulse signal of a VTR. The DC voltage source 11 is for biasing an input signal in, which is a reproduced output signal of a control pulse signal of a VTR, to a voltage vB. This voltage v[
The input signal vin biased at 3 is supplied to the maximum voltage detection circuit 12 and the minimum N pressure detection circuit 13, and is also supplied to the non-inverting input terminal of the operational amplifier 14 and the inverting input terminal of the operational amplifier 15, which constitute a comparator, respectively. be done.
上記最小Ｎ圧検出回路１２及び最小電圧検出回路１３は
入力信号ｖｉｎの最大電圧及び最小電圧を検出し、保持
するものであり、両回路の出力端子間には直列接続され
た４個の抵抗１６〜１９からなる閾値電圧発生回路２０
が接続されている。従って、最大電圧検出回路１２で検
出、保持された最大電圧ＶＭＡＸは閾値電圧発生回路２
０内の抵抗１６の一端に供給され、最小電圧検出回路１
３で検出、保持された最小電圧ＶＭＩＮは閾値Ｎ圧発住
回路２０内の抵抗１９の一端に供給される。この閾値電
圧発生回路２０は、抵抗１６と１７の直列接続点から高
レベル側の閾値電圧ＶＡを発生し、かつ抵抗１８と１９
の直列接続点から低レベル側の閾値電圧ＶＣを発生する
。The minimum N pressure detection circuit 12 and the minimum voltage detection circuit 13 detect and hold the maximum voltage and minimum voltage of the input signal vin, and four resistors 16 are connected in series between the output terminals of both circuits. Threshold voltage generation circuit 20 consisting of ~19
is connected. Therefore, the maximum voltage VMAX detected and held by the maximum voltage detection circuit 12 is the threshold voltage generation circuit 2.
0 and is supplied to one end of the resistor 16 within the minimum voltage detection circuit 1
The minimum voltage VMIN detected and held at step 3 is supplied to one end of a resistor 19 in the threshold N voltage generating circuit 20. This threshold voltage generation circuit 20 generates a high-level threshold voltage VA from the series connection point of resistors 16 and 17, and
A low-level threshold voltage VC is generated from the series connection point of .
そして、高レベル側の閾値電圧ＶＡは上記演算増幅器１
４の反転入力端子に供給され、低レベル側の閾値電圧ｖ
Ｃは上記演算増幅器１５の非反転入力端子に供給される
。上記両演算増幅器１４．１５の各出力は、ＲＳＳフリ
ップフロラ回路２１にセラミル入力Ｓ及びリセット人力
Ｒとして供給され、このフリップフロップ回路２１から
は変換されたディジタル信号５Ｏｕｔが出力される。The threshold voltage VA on the high level side is the operational amplifier 1.
4, the low level side threshold voltage v
C is supplied to the non-inverting input terminal of the operational amplifier 15. The outputs of the operational amplifiers 14 and 15 are supplied to an RSS flip-flop circuit 21 as a ceramic input S and a reset input R, and the flip-flop circuit 21 outputs a converted digital signal 5Out.
なお、上記閾値電圧発生回路２０内の４個の抵抗１６〜
１９は例えば全て同値であっても良く、あるいは必要に
応じて異ならせることもできる。Note that the four resistors 16 to 16 in the threshold voltage generation circuit 20
19 may all have the same value, for example, or may be different as necessary.
次に上記構成でなる回路の動作を説明する。Next, the operation of the circuit having the above configuration will be explained.
いま、第２図のタイミングチャートに示すように、コン
トロールパルス信号の再生出力信号としての入力信号ｖ
ｉｎの正負両極性のパルスのピーク電圧が大ぎい場合、
最大電圧検出回路１２で検出、保持される最大電圧ｖＭ
ＡＸは高く、最小電圧検出回路１３で検出、保持される
最小電圧ＶＩＶＩＩＮは低くなり、閾値電圧発生回路２
０で発生される高レベル側の閾値電圧ｖＡと低レベル側
のＲ値電圧ＶＣとの間の電圧、すなわちヒステリシス電
圧は比較的大きくなる。このとき、演算増幅器１４の出
力Ｓは入力信号ｖ曲の電圧が高レベル側の同値電圧ＶＡ
よりも高くなれば゛′１゛ルベル、それ以外のときには
″′Ｏ″レベルとなり、演算増幅器１５の出力Ｒは入力
信号ｖｉｎの電圧が低レベル側の閾値電圧ＶＣよりも低
くなれば゛１″レベル、それ以外のときには゛′Ｏ″レ
ベルになる。従って、入力信号ｖｉｎは正しくディジタ
ル信号３０ｕｔに変換される。Now, as shown in the timing chart of FIG. 2, the input signal v as the reproduction output signal of the control pulse signal
If the peak voltage of the positive and negative polarity pulses of in is too large,
Maximum voltage vM detected and held by the maximum voltage detection circuit 12
AX is high, the minimum voltage VIVIIN detected and held by the minimum voltage detection circuit 13 is low, and the threshold voltage generation circuit 2
The voltage between the high-level threshold voltage vA generated at 0 and the low-level R value voltage VC, that is, the hysteresis voltage, becomes relatively large. At this time, the output S of the operational amplifier 14 is the equivalent voltage VA at which the voltage of the input signal v is on the high level side.
If the voltage of the input signal vin becomes lower than the threshold voltage VC on the low level side, the output R of the operational amplifier 15 becomes ``1'' level. Otherwise, it becomes ``O'' level. level, otherwise it becomes 'O' level. Therefore, the input signal vin is correctly converted into the digital signal 30ut.
一方、第３図のタイミングチャートに示すように、コン
トロールパルス信号の再生出力信号としての入力信号ｖ
ｉｎの正負両極性のパルスのピーク電圧が小さい場合、
最大電圧検出回路１２で検出、保持される最大電圧ＶＭ
ＡＸは第２図の場合よりは低くなり、最小電圧検出回路
１３て検出、保持される最小電圧ＶＭｒＮは第２図の場
合よりは高くなる。このため、ヒステリシス電圧は第２
図の場合に比べて小さくなる。一般に、コン１〜ロール
パルス信号の再生出力信号の正負両極性のパルスのピー
ク電圧がｔＪ＼さくなるような場合には、ノイズ成分の
信号レベルも相対的に低下する。従って、この場合にも
図示のように入力信号ｖｉｎが正しいディジタル信号３
ｏｕｔに変換される。On the other hand, as shown in the timing chart of FIG. 3, the input signal v as the reproduction output signal of the control pulse signal
If the peak voltage of the positive and negative polarity pulses of in is small,
Maximum voltage VM detected and held by maximum voltage detection circuit 12
AX is lower than in the case of FIG. 2, and the minimum voltage VMrN detected and held by the minimum voltage detection circuit 13 is higher than in the case of FIG. Therefore, the hysteresis voltage is
It is smaller than the case shown in the figure. Generally, when the peak voltage of the positive and negative polarity pulses of the reproduced output signals of the control 1 to roll pulse signals decreases tJ\, the signal level of the noise component also decreases relatively. Therefore, in this case as well, the input signal vin is the correct digital signal 3 as shown in the figure.
Converted to out.
このにうに上記実施例回路によれば、入力信号ｖｉｎの
ピークレベルに応じて２種の閾値電圧の値が自動的に設
定されるので閾値電圧の設定が不要であり、しかも入力
信号ｖｉｎのピークレベルに応じてヒステリシス電圧を
異ならせるようにしたので、入力信号が変動しても誤動
作を起こす恐れがない。In this way, according to the above embodiment circuit, two types of threshold voltage values are automatically set according to the peak level of the input signal vin, so there is no need to set the threshold voltage, and moreover, the peak level of the input signal vin Since the hysteresis voltage is varied depending on the level, there is no risk of malfunction even if the input signal fluctuates.
第４図は上記実施例回路の最大電圧検出回路１２の具体
的な構成を示す回路図である。この回路は、ベースに入
力信号■団が供給されるｎ ｐ ｎ ｌ−ランジスタ３
１を介してコンデンサ３２を充電制御すると共に、コン
デンサ３２を定電流ｌ１３３の一定電流で放電制御する
ことにｊ；す、コンデンサ３２に入力信号ｖｉｎの最大
電圧ＶＭＡＸが生じるようにしだものである。FIG. 4 is a circuit diagram showing a specific configuration of the maximum voltage detection circuit 12 of the above embodiment circuit. This circuit consists of an n p n l transistor 3 whose base is supplied with an input signal group.
1, the capacitor 32 is charged and discharged using a constant current l133, so that the maximum voltage VMAX of the input signal vin is generated in the capacitor 32.
第５図は上記実施例回路の最小電圧検出回路１３の具体
的な構成を示す回路図である。この回路は、定電流源４
１の一定電流でコンデンサ４２を充電制御すると共に、
ベースに入力信号ｖｉｎが供給されるｐｎｐ＋−ランジ
スタ４３を介してこのコンデンサ４２を放電制御するこ
とにより、コンデンサ４２に入力信号＼１１１）の最小
電圧ＶＭＩＮが生じるようにしたものである。FIG. 5 is a circuit diagram showing a specific configuration of the minimum voltage detection circuit 13 of the above embodiment circuit. This circuit consists of constant current source 4
While controlling the charging of the capacitor 42 with a constant current of 1,
By controlling the discharge of this capacitor 42 via a pnp+- transistor 43 whose base is supplied with an input signal vin, the minimum voltage VMIN of the input signal \111) is generated in the capacitor 42.
第６図は上記実施例回路のＲＳフリップ７０ツブ回路２
１の具体的な構成を示す回路図である。この回路は入出
力端子間が交差接続された２個の２人力ＮＡＮＤグー１
〜５１．５２と、前記演算増幅器１４゜１５の出力Ｓ、
Ｒそれぞれを反転して上記各ＮＡＮＤゲー１へ５１．５
２に供給するインバータ５３．５４とから構成されてい
る。Figure 6 shows the RS flip 70 tube circuit 2 of the above embodiment circuit.
FIG. 1 is a circuit diagram showing a specific configuration of FIG. This circuit consists of two 2-power NAND circuits with input and output terminals cross-connected.
~51.52 and the output S of the operational amplifier 14°15,
Invert each R and add 51.5 to each NAND game 1 above.
2 and inverters 53 and 54.
なお、この発明は上記の実施例に限定されるものではな
く種々の変形が可能であることはいうまでもない。例え
ばト記実施例回路では、閾値電圧発生回路２０が直列接
続された４個の抵抗１６〜１９で構成される場合につい
て説明したが、これは抵抗１７と１８の代わりに１個の
抵抗を設けるようにしてもよい。また、最大電圧検出回
路１２及び最小電圧検出回路１３それぞれも例えばディ
ジタル回路等で構成するようにしてよい。It goes without saying that the present invention is not limited to the above-described embodiments, and that various modifications can be made. For example, in the example circuit described above, the threshold voltage generation circuit 20 is composed of four resistors 16 to 19 connected in series, but in this case, one resistor is provided in place of the resistors 17 and 18. You can do it like this. Furthermore, each of the maximum voltage detection circuit 12 and the minimum voltage detection circuit 13 may be configured with, for example, a digital circuit.
［発明の効宋コ
以上説明したようにこの発明によれば、閾値電圧の設定
が不要であり、かつ入力信号の電圧が変動しても誤動作
を起こすことのないシュミツ１−トリガ回路が提供でき
る。[Effects of the Invention] As explained above, according to the present invention, it is possible to provide a Schmidts 1-trigger circuit that does not require setting of a threshold voltage and does not malfunction even if the input signal voltage fluctuates. .
第１図はこの発明の一実施例による構成を示ず回路図、
第２図及び第３図はそれぞれ上記実施例回路の動作を説
明するためのタイミングヂャート、第４図ないし第６図
はそれぞれ上記実施例回路の各部分の一具体例を示す回
路図、第１図は従来の回路図、第８図ないし第１０図は
それぞれ従来回路の動作を示ず′タイミングチャー１へ
である。
１１・・・直流電圧源、１２・・・最大電圧検出回路、
１３・・・最小電圧検出回路、１４．１５・・・演算増
幅器、１６へ・１９・・・抵抗、２０・・・閾値電圧発
生回路、２１・・・ＲＳＳフリップフロラ回路。
出願人代理人 弁理士 鈴 江 武 彦の ニ
（′ｗ′）トFIG. 1 is a circuit diagram showing a configuration according to an embodiment of the present invention;
2 and 3 are timing charts for explaining the operation of the above embodiment circuit, respectively, and FIGS. 4 to 6 are circuit diagrams showing one specific example of each part of the above embodiment circuit, respectively. FIG. 1 is a conventional circuit diagram, and FIGS. 8 to 10 each do not show the operation of the conventional circuit, but are shown in timing chart 1. 11... DC voltage source, 12... Maximum voltage detection circuit,
13... Minimum voltage detection circuit, 14.15... Operational amplifier, 16 to 19... Resistor, 20... Threshold voltage generation circuit, 21... RSS flip Flora circuit. Applicant's representative Patent attorney Takehiko Suzue ('w')
Claims (1)
手段と、 入力信号の最小電圧を検出し、保持する最小電圧検出手
段と、 直列接続された３個以上の抵抗からなり、上記最大電圧
が一端に供給され、上記最小電圧値が他端に供給され、
これら各抵抗の直列接続点から高レベル側の閾値電圧並
びに低レベル側の閾値電圧を発生する閾値電圧発生手段
と、 上記入力信号の電圧と上記高レベル側の閾値電圧とを比
較する第１の電圧比較手段と、 上記入力信号の電圧と上記低レベル側の閾値電圧とを比
較する第２の電圧比較手段と、 上記第１及び第２の電圧比較手段の出力に基づいて制御
されるフリップフロップ回路とを具備したことを特徴と
するシユミットトリガ回路。[Claims] Maximum voltage detection means for detecting and holding the maximum voltage of an input signal; Minimum voltage detection means for detecting and holding the minimum voltage of the input signal; and three or more resistors connected in series. and the above maximum voltage is supplied to one end, the above minimum voltage value is supplied to the other end,
threshold voltage generating means for generating a high level threshold voltage and a low level threshold voltage from the series connection point of each of these resistors; voltage comparison means; second voltage comparison means for comparing the voltage of the input signal with the low-level threshold voltage; and a flip-flop controlled based on the outputs of the first and second voltage comparison means. A Schmitt trigger circuit characterized by comprising a circuit.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63095009A JPH01265718A (en) | 1988-04-18 | 1988-04-18 | Schmitt trigger circuit |
| US07/338,795 US5003196A (en) | 1988-04-18 | 1989-04-17 | Wave shaping circuit having a maximum voltage detector and a minimum voltage detector |
| KR1019890005086A KR920003447B1 (en) | 1988-04-18 | 1989-04-18 | Schmittrigger circuit |
| EP89106948A EP0338517A3 (en) | 1988-04-18 | 1989-04-18 | Schmitt trigger circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63095009A JPH01265718A (en) | 1988-04-18 | 1988-04-18 | Schmitt trigger circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01265718A true JPH01265718A (en) | 1989-10-23 |
Family
ID=14125940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63095009A Pending JPH01265718A (en) | 1988-04-18 | 1988-04-18 | Schmitt trigger circuit |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5003196A (en) |
| EP (1) | EP0338517A3 (en) |
| JP (1) | JPH01265718A (en) |
| KR (1) | KR920003447B1 (en) |
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| JP2009200944A (en) * | 2008-02-22 | 2009-09-03 | Oki Semiconductor Co Ltd | Hysteresis comparator |
Also Published As
| Publication number | Publication date |
|---|---|
| KR920003447B1 (en) | 1992-05-01 |
| KR890016758A (en) | 1989-11-30 |
| EP0338517A3 (en) | 1990-03-14 |
| US5003196A (en) | 1991-03-26 |
| EP0338517A2 (en) | 1989-10-25 |
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