JPS62130013A - Delay device - Google Patents

Abstract

PURPOSE:To realize a delay device having less variance of delay time by switching a charging current of an integration circuit so as to have only to use one integration circuit in obtaining an output signal having a different delay time from one input signal. CONSTITUTION:When the input signal is at a high level, since a current flows through a switch 2 from a constant current source 4, no electric charge is stored in a capacitive element 3. When the input signal reaches a low level, the switch 2 is opened and the potential at a point B rises. The potentials of an inverting input terminal of the 1st comparator circuit 6 and the 2nd comparator circuit 7 are denoted as V1, V2 respectively, and when the potential at the point B reaches the potential V1 at a period T1 after the input signal goes to a low level, the output of the comparator circuit 6 goes to a high level and a switch 13 is closed, then a current corresponding to a difference between the current fed from a constant current source 4 and the current from a constant current source 14 is stored in the capacitive element 3. Thus, the charging current is decreased in comparison with the period T1 and the rise in the potential is relaxed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a delay device used when obtaining two or more output signals having mutually different delay times from one input signal.

Figure 3 is a block diagram showing an example of a conventional delay device. In FIG. 3, a switch 2 that is opened and closed by a signal applied to an input terminal 1 has one end grounded, the other end grounded via a capacitive element 3, and connected to one end of a constant current source 4. There is. The other end of the constant current source 4 is connected to a power supply terminal 6. Switch 2, capacitive element 3, and constant current source 4
The connection point is connected to the in-phase input terminals of the first comparison circuit 6 and the second comparison circuit 7. The negative phase input terminal of the first comparator circuit 6 is grounded via a resistor 8, and is also grounded via a resistor 9.
is connected to the negative phase input terminal of the second comparator circuit 7 via
Furthermore, it is connected to a power supply terminal 6 via a resistor 1Q. The outputs of the first comparator circuit 6 and the second comparator circuit 7 are connected to output terminals 11 and 12, respectively.

The operation of the conventional delay device configured as described above will be explained. Here, it is assumed that the switch 2 is closed when the signal supplied to the input terminal 1 is at a high level.

Consider a case where an input signal as shown in FIG. 4 is supplied to the input terminal 1. First, when the input signal is at a high level, a current flows from the constant current source 4 through the switch 2, so that no charge is accumulated in the capacitive element 3.

Next, when the input signal is at a low level, the switch 2 is open, so that all the current supplied from the constant current source 4 is stored in the capacitive element 3. That is, the capacitive element 3 and the constant current source 4 operate as an integrating circuit.

Therefore, the potential difference between both ends of the capacitive element 3, that is, the potential at point B in FIG. 3 becomes as shown in FIG. 4(B).

Here, the potentials of the negative phase input terminals of the first comparison circuit 6 and the second comparison circuit 7 are set to 1. v2 (obviously vl<■2 from Figure 3), and if the potential is as shown in Figure 4 (B), the output signals obtained at the output terminals 11 and 12 are as shown in Figure 4 (C), respectively. , (L)), T1 . For a signal whose level changes with a delay of T2 period, the relationship between delay times T1 and T2 is as shown in the following equation.

T1: T2= Vl: V2---(1) Problems to be Solved by the Invention When the ratio of the required delay time T and T2 is relatively large, from equation (1), It is necessary to increase the ratio of potentials (1) and (2), but since there are generally many restrictions on the potential of the power supply terminal, the value of (1) is made small. However, in reality, the comparison circuits 6 and 7 have a finite input impedance and a so-called dead zone in which the output is not uniquely determined. Since it is not necessarily zero, the value of T1 is often different from the design value, and the range of variation when mass-produced is T2.
There was a problem that the value was larger than the value of .

Therefore, in reality, time constant circuits are often constructed independently, leading to an increase in the number of components or an increase in chip area when the time constant circuits are constructed on an integrated circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a delay device that solves the above problems by switching the charging current of the integrating circuit between the T1 period and the period thereafter.

Means for Solving the Problems The present invention provides a switch circuit that is opened and closed by an input signal, an integration circuit that is reset by the switch circuit and whose charging time constant can be switched, and an output level of the integration circuit that is set to a first level. a first comparison circuit that detects the time when a predetermined value is reached;
a second comparison circuit that detects a time when the output level of the integration circuit reaches a second predetermined value that is greater than the first predetermined value; It is configured to switch the charging time constant of the circuit.

Effect The present invention has the above-described configuration, and the first and second
It is possible to bring the reference voltages of the comparison circuits closer to each other than in the past, and the difference in the range of variation in delay time between the two can be reduced.

Embodiments Hereinafter, embodiments of a delay device according to the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of the same embodiment. In FIG. 1, a switch 2 that is opened and closed by a signal applied to an input terminal 1 has one end grounded, the other end grounded via a capacitive element 3, and one end of a constant current source 4 connected to a switch 13. Connected to the connection point with one end. The other end of the constant current source 4 is connected to the power supply terminal 5, and the other end of the switch 13 is grounded via the constant current source 14. Switch 2 and capacitive element 3
The connection point between the constant current source 4 and the switch 13 is connected to the in-phase input terminals of the first comparison circuit 6 and the second comparison circuit 7. The negative phase input terminal of the first comparator circuit 6 is grounded via a resistor 8 and connected to the second comparator circuit 7 via a resistor 9.
, and further connected to the power supply terminal 5 via a resistor 1o. The output of the first comparator circuit 6 is connected to the control terminal of the switch 13 and also to the output terminal 11 , and the output of the second comparator circuit 7 is connected to the output terminal 12 .

Regarding the delay device of this embodiment configured as above,
The operation will be explained below using FIGS. 1 and 2. Here, switch 2 and switch 13 are assumed to be closed when their respective control signals are at high level.

FIG. 2 is a waveform diagram for explaining the operation of the embodiment of the present invention shown in FIG. 1. Let us consider the case where an input signal as shown in FIG. 2 (5) is supplied.

First, when the input signal is at a high level, a current flows from the constant current source 4 through the switch 2, so that no charge is accumulated in the capacitive element 3. Therefore, the potential difference between both ends of the capacitive element 3, that is, the potential at point B in FIG. 1 is at a low level.

Next, when the input signal changes from high level to low level, the switch 2 opens and all the current supplied from the constant current source 4 is accumulated in the capacitive element 3, so the potential at point B in Figure 1 changes to CB in Figure 2. ) to rise like this.

Here, the potentials of the negative phase input terminals of the first comparison circuit 6 and the second comparison circuit 7 are set to 1. Assume that the voltage is v2 (as shown in FIG. 1, <v2), and the potential is as shown in FIG. 2(B).

T1 after the input signal changes from high level to low level
After the period, when the potential at point B in FIG. 1 reaches V, the output of the first comparison circuit 6 changes from low level to high level as shown in FIG.
Electrician supplied by. A current corresponding to the difference between the current value and the current value supplied to the constant current source 14 is accumulated in the capacitive element 3. Therefore, for example, the current ratio between the constant current source 4 and the constant current source 14 should be adjusted. :I, 4=5:4 ・・・・・・
(2), the charging current of the capacitive element 3 decreases to 115 compared to the 11th period, and the slope becomes gentler as shown in FIG. 2(B).

Furthermore, when the potential at point B in FIG. 1 reaches V after one voice after the input signal changes from the NO level to the low level, the output of the comparator circuit 7 in FIG. 2 goes to the low level as shown in FIG. It becomes a no-i level. At this time, vl:v2=1=2 (3
), then (2) t (3) + (4) r < ni) formula, T, I = (T2-T,)・k. 15 ・
・・・・−(6) Therefore, T1:T2=1:6 ・・・・・・(
η. That is, according to this embodiment, (3)!
As can be seen from equation ('r), it is possible to increase the ratio of delay times while keeping the ratio of potentials at the negative phase input terminals of the comparator circuit relatively small. With respect to variations in dead band width and variations in on-resistance of switches, it is possible to make the range of variation in delay time smaller than before.

Effects of the Invention As described above, according to the present invention, even when two or more output signals having different delay times are obtained from one input signal, the charging current of the integrating circuit is controlled by the output signal of the comparator circuit. By configuring the circuit to switch, it is possible to realize a delay device with small variation in fl=31E time by using only one integrating circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a delay device according to the present invention, FIG. 2 is a waveform diagram for explaining its operation, FIG. 3 is a circuit diagram showing an example of a conventional delay device, and FIG. 4 is a waveform diagram for explaining the operation. 1... Input terminal, 2, 13... Switch, 3... Capacitive element, 4, 14... Constant current source, 6...・Power supply terminal, 6, 7...
... Comparison circuit, 8, 9, 10... Resistor, 11.
12...Output terminal. Name of agent: Patent attorney Toshio Nakao and one other person9
LD --- 1, 7 3 NIQ -- One bottom I Figure 2 Man-11-1 Figure 3 Figure 4

Claims (1)

[Claims] A switch circuit that is opened and closed by an input signal, an integration circuit that is reset by the switch circuit and whose charging time constant can be switched, and a time when the output level of the integration circuit reaches a first predetermined value is detected. a first comparison circuit; and a second comparison circuit that detects a time when the output level of the integration circuit reaches a second predetermined value that is greater than the first predetermined value; A delay device characterized in that the charging time constant of the integrating circuit is switched by the output of the comparing circuit.