JPS60113521A - Timing circuit - Google Patents

Abstract

PURPOSE:To obtain assuredly a timing difference output by comparing the output of a time constant circuit with two different reference voltages by a comparator. CONSTITUTION:A power supply V is impressed and divided by resistances R3- R5, and reference voltages Va and Vb (Va<Vb) are supplied to an input terminal at one side of comparators IC1 and IC2 respectively. At the same time, a capacitor C is charged via a variable resistance RV1. The output of the IC1 is inverted after a time point Ta when the voltage of the capacitor C exceeds the voltage Va. Then the output of the IC2 is inverted after a time point Tb when the charged voltage exceeds the voltage Vb. Then a timing difference Tb-Ta is obtained. An optional timing difference is obtained by varying the value of a variable resistance RV3.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) 1 Technical Field of the Invention The present invention relates to a timing circuit, and particularly to a timing circuit that generates a plurality of timing differences.

(b), Prior art - Problems The timing circuit referred to here is, for example, two terminals A,...
This is a circuit in which there is a terminal B, and the difference in time when terminals A and B change from OFF to ON is positive (or negative) and takes a specified value.

Such timing circuits are generally widely used in circuits for protecting the drooping characteristics of DC-DC converters.

FIG. 1 is a circuit diagram showing an embodiment of a conventional timing circuit that generates a plurality of timing differences like this.

FIG. 2 is a diagram for explaining the operation of the circuit shown in FIG. 1.

In the figure, R1 and R2 are resistors, CI and C2 are capacitors, VRI and VH2 are variable resistors, ICI and IC2, respectively.
are voltage comparators, Vl and V2 are voltage comparators ICI, respectively.
, is the output of IC2.

The present invention will be described in detail below with reference to the drawings. Note that FIG. 1 shows a circuit for creating one timing difference. For example, in order to create two timing differences, it is sufficient to prepare one more set of variable resistors, capacitors, and voltage comparators.

In FIG. 1, when the power supply voltage (2) is applied to the terminal in, the terminal voltage of the resistor R2 is a voltage obtained by dividing the power supply voltage V to the ratio of the resistors R1 and R2, and takes a constant value.

On the other hand, the terminal voltage Vcl of capacitor C1 is (al
As shown in , the terminal voltage Vcl of capacitor C1 increases with a time constant determined by variable resistor VRI and capacitor CI.
When V becomes larger than the terminal voltage of resistor R2, the output voltage V1 of voltage comparator IC1 changes from 0'' to l''.

After the power supply voltage ■ is applied to the terminal in, the output voltage V1 becomes “
The time Tel until it becomes 1'' can be adjusted by adjusting the variable resistor VR1.

Similarly, the time Tc until the output voltage ■2 of the voltage comparator IC2 changes from "0" to "1" by adjusting the variable resistor VR2.
2 can be adjusted.

If the variable resistor VR1 and the variable resistor VR2 are set so that Tc 2 Tc I = ΔT as shown above, the output voltage 2 of the voltage comparator TC2 will always be ΔT less than the output voltage V1 of the voltage comparator ICI. It is possible to set the value to 1'' at a later point in time.

However, the conventional timing circuit described above uses two variable resistors.
l! The disadvantage is that the adjustment is complicated because it creates a single time difference.

(C)3 Objectives of the Invention The objectives of the present invention are to eliminate the above-mentioned drawbacks of the prior art;
It is an object of the present invention to provide a timing circuit that can more simply and reliably create a timing difference.

(d) 8 Structure of the Invention According to the present invention, the above objects include a bleeder circuit consisting of a plurality of N series resistors, a series circuit of a variable resistor and a capacitor,
and in a timing circuit composed of the plurality of N-1 voltage comparators, the bleeder circuit and the series circuit are connected in parallel to apply a DC power supply voltage, and the terminal voltage of the capacitor is set to the plurality of N-1 voltage comparators. Commonly connected to one input terminal of each of one voltage comparator, and connecting terminal between each resistor constituting the bleeder circuit to other input terminal of each of the plurality of N-1 voltage comparators. This is achieved by providing a timing circuit characterized by the following.

(e) 6 Embodiments of the Invention FIG. 3 is a circuit diagram showing an embodiment of a timing circuit according to the present invention.

- FIG. 4 is a diagram for explaining the operation of the circuit shown in FIG. 3.

In the figure, resistors R3, R4, and R5 are resistors, C is a capacitor, RV3 is a variable resistor, ICI and IC2 are voltage comparators, and Vl and 2 are outputs of voltage comparators ICI and lc2, respectively.

The present invention will be described in detail below with reference to the drawings.

In Fig. 3, when the power supply voltage V is applied to the terminal in, the power supply voltage ■ is divided by the resistors R3, R4, and R5, and the terminal voltage Va of the resistor R3 and the voltage vb at the connection point of the resistors R3 and R4 are shown. takes a constant value.

Moreover, voltage vb is always larger by a constant voltage consisting of voltage Va.

This voltage Va is applied to one of the inputs of the voltage comparator ICI, and the voltage vb is applied to one of the inputs of the voltage comparator IC2.

On the other hand, the charging current flows through the capacitor C via the variable resistor RV3.
The terminal voltage Vc of the capacitor C increases sequentially according to a time constant determined by the capacitor C and the variable resistor RV3, and when it first becomes larger than the voltage Va, the voltage comparator IC
The output voltage V1 of the voltage comparator IC2 changes from "0" to "1" at the next point in time when it becomes larger than the voltage vb.

This pattern is shown in FIG. 4 (a) to (C1).

+a) in FIG. 4 is a diagram showing a situation in which the terminal voltage Vc of the capacitor C increases with time.

(bl in FIG. 4 is a diagram explaining the situation of the output voltage V1 of the voltage comparator ICI. After the power supply voltage V is applied to the terminal in, the output voltage 1 of the voltage comparator ICI changes from '0'' to '0''.
Let Ta be the time taken until the value changes to 1''.

(C) of FIG. 4 is a diagram explaining the situation of the output voltage ■2 of the voltage comparator IC2. After the power supply voltage ■ is applied to the terminal in, the output voltage ■2 of the voltage comparator IC2 becomes "0". from 1
The time required for the change to change to `` is Tb.

In this case, "I'a<'Y'b" and ΔT(ΔT
-Tb-Ta) is determined by variable resistor RV3.

(f) Effects of the Invention As described in detail, the present invention has the great effect of realizing a timing circuit that can more easily and reliably create a timing difference.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a conventional timing circuit that generates a plurality of timing differences like this. FIG. 2 is a diagram for explaining the operation of the circuit shown in FIG. 1. FIG. 3 is a circuit diagram showing one embodiment of a timing circuit according to the present invention. FIG. 4 is a diagram for explaining the operation of the circuit shown in FIG. 3. In the figure, resistors R1 to R5 are each a resistor, C, CI, and C2 are each a capacitor, RVI to RV3 & are each a variable resistor, and an IC
I and IC2 are voltage comparators, respectively, and ■1 and ■2 are outputs of the voltage comparators ICI and IC2, respectively.

Claims (1)

[Claims] In a timing circuit composed of a bleeder circuit consisting of a plurality of N series resistors, a series circuit of a variable resistor and a capacitor, and a plurality of N=1 voltage comparators, the bleeder circuit and the series circuit are connected in parallel. applying a DC power supply voltage, connecting the terminal voltage of the capacitor in common to one input terminal of each of the plurality of N-1 voltage comparators, and connecting terminals between the respective resistors constituting the bleeder circuit. plural N-
A timing circuit characterized in that it is connected to each other input terminal of a voltage comparator.