JPS6354003A - Pseudo sinusoidal wave generating circuit - Google Patents

Abstract

PURPOSE:To obtain a pseudo sinusoidal wave with a simple circuit by constituting the titled pseudo sinusoidal wave generating circuit by the combination of a voltage division circuit, a multiplexer, an operational amplifier and an integration capacitor. CONSTITUTION:In generating a pseudo sinusoidal wave 12, a pseudo COS wave 13 comprising step voltages is outputted from the multiplexer 12. The pseudo COS wave 13 is a voltage consisting of 8-step and obtained by turning on switches S1-S8 sequentially at a prescribed speed. When a 1st switch S1 is turned on during periods t0-t1, a voltage at s DC power terminal 1 is divided by resistors R1-R9, a 1st stage voltage V1 is obtained at an output line 2a and becomes an input to the operational amplifier 4. A voltage VR higher than the voltage V1 is impressed to a noninverting input terminal 4b. A charging current of the integration capacitor 7 flows through a circuit comprising an output terminal 4c of the operational amplifier 4, the integration capacitor 7, an input resistor 5, the switch S1 and the resistor R1 and the charging voltage of the capacitor 7 rises gradually. Thus, a pseudo sinusoidal wave with excellent approximity is obtained by integrating the step wave pseudo COS wave 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pseudo sine wave generation circuit suitable for obtaining a pseudo sine wave necessary when forming a PWM control signal for an inverter.

[Conventional technology]

A method of forming a signal for PWM control of an inverter based on a comparison between a sine wave and a triangular wave is well known. Conventionally, to obtain this kind of sine wave,? Generate a sinusoidal staircase wave using a voltage dividing resistor circuit of J number, or
Alternatively, memo IJK sine wave data was written, read out, and converted into D/As.

[Problem that the invention seeks to solve]

By the way, in order to generate a staircase wave in the former sine wave, multiple resistor voltage divider circuits and filter circuits are required.
The circuit configuration has become complicated. In the latter method using memory, the circuit becomes complicated and expensive due to the use of memory and a D/A converter.

Therefore, one object of the present invention is to generate a pseudo sine wave with a simple circuit configuration.

[Means for solving problems]

In order to solve the above problems and achieve the above objects, the present invention has a plurality of divided voltage output lines that divide and output the DC power supply voltage, and generates a pseudo COS waveform in the output stage of the multiplexer described later. A voltage dividing resistor circuit in which the voltage values of the plurality of divided voltage output lines are set so as to be able to obtain a base sII voltage supply line for supplying the same voltage as the center voltage in the voltage dividing resistor circuit; one input terminal is connected to the multiplexer via the input resistor, and the other input terminal is connected to the multiplexer through the input resistor; The present invention relates to a pseudo sine wave generation circuit comprising a next operational amplifier connected to the standard heavy pressure supply line, and a next term capacitor connected between one input terminal and output terminal of the operational amplifier. Note that the output line and reference voltage supply line in the present invention mean not only the respective transmission lines but also the respective output terminals and the like.

[For production]

A pseudo COS wave is generated from the multiplexer according to the present invention, and this wave is input to one input terminal of the operational amplifier.

Since the center voltage of the resistive voltage divider circuit is input as the reference voltage to the other input terminal, the direction of the current flowing through the integrating capacitor V differs before and after the pseudo ωs@ crosses the reference voltage. During this half-sine wave O''~906~906 interval, a current flows in the direction of m through the integrating capacitor, and the output voltage of the operational amplifier gradually increases from the reference voltage, 90'.
peaks at In the 90° to 180' interval, a current flows through the integrating capacitor in the m2 direction, which is opposite to the ]th direction, so that the output voltage of the operational amplifier gradually decreases.

As a result, the sine wave is close to 1. -1137 type can be easily obtained. By periodically repeating the divided voltage output selection operation by the multiplexer, a pseudo sine wave half wave is repeatedly obtained.

〔Example〕

Next, a pseudo sine wave generating circuit according to an embodiment of the present invention will be explained based on FIGS. 1 and 2. A voltage dividing resistor circuit tI consisting of a series circuit of first to ninth resistors R1 to R1 is connected between the ground and the DC power supply terminal (1). The value of each resistor R, ~R9 is 1.7 to obtain a pseudo COS wave.
．． 5.13, 18.20, 18, 13.7.5.1 (k
Ω). However, in order to obtain a reference voltage, the fifth resistor R5 is divided into 1c10, R5 of Ω, and Rgb of ]OkΩ. The first to eighth output lines L, -L are connected to each voltage division 4 of the first to ninth resistors R0 to R9.

The multiplexer (2) is connected to the eighth output line L1.
7' (first to eighth switches 81
~S8 and a control circuit for sequentially turning on the S8 (
3).

A multiplexer output line (2a) consisting of a common connection line of the first to eighth switches 81 to 81 is connected to an operational amplifier (
4) is connected to the inverting input terminal (4a) via an input resistor r51. Non-inverting input terminal of operational amplifier (4) (
4h) is connected between the center voltage imaginary part of the voltage dividing resistor circuit (2), ie, the resistors R3a and 1(, b), by the reference constant voltage supply line (6).The operational amplifier (410 inverting input terminal ( An integrating capacitor (71) is connected between 4a) and the output terminal (4C), and an R return resistor +81 (
91 is connected. QG is a capacitor for adjusting frequency characteristics, and is connected between the connection point between the resistors (8) and (9) and the ground.

αυ is a level control circuit, which is connected to the output terminal (4c) of the operational amplifier (4). This level control circuit α
υ has a half-sine wave zero point adjustment and amplitude adjustment function.

When the pseudo sine wave α2 shown in FIG. 2 is generated by the circuit shown in FIG. 1, a pseudo COS wave α3 consisting of a staircase voltage is outputted from the multiplexer (2). Pseudo COS wave a3
are voltages in eight stages from the first constant voltage vI to the eighth voltage v8, and are obtained by sequentially turning on the switches S+''-8s at a constant speed. That is, from to to t1, the switch S1 is turned on. On, turn on switch S2 from t1 to t2,
Switch S3 is turned on from t2 to t3, switch S4 is turned on from t3 to t4, and switch S5 is turned on from i4 to ts.

This is obtained by turning on the switch S6 from tII to t6, turning on the switch S7 from t6 to t7, and turning on the switch S8 from t7 to t8. Note that the tacts interval corresponds to 180° of the sine wave, to ~ tl, tl ~ t2...
The on period of each switch such as . . . corresponds to 22.5.

When the first switch S1 is turned on during the to'''-t1 period, the voltage at the DC 11 cool terminal (11 is divided by the resistors R1 to R0, and the first stage voltage vl is obtained from the output line (2a) K. .

This becomes the input to the operational amplifier (4). At this time, VR higher than vl is applied to the non-inverting input terminal (4h) of the operational amplifier (4). Operational amplifier (41 is an inverting input terminal (4a) based on the principle of imaginary short)
The output terminal (4C) of the operational amplifier (4) operates so that the potential of the operational amplifier (4) becomes equal to the potential of the non-inverting input terminal (4b).
), an integrating capacitor (71), an input resistor (5), a switch S, and a resistor R1. In the circuit consisting of an integrating capacitor (71), a charge 1it current of the integrating capacitor (71) flows, and a charge 11 of the integrating capacitor (7) flows!
The pressure gradually increases. Switch 8225 from 11 to t2
, the second stage voltage v2 becomes the input voltage of the operational amplifier (41). Therefore, in the 5tl-'! period, the integrating capacitor (7) has a slope corresponding to the second stage voltage V2.
voltage increases. The input voltage from t1 to t4 is based on
! i! Since the voltage is lower than the current voltage, the integrating capacitor (7) is charged so that the output terminal (4c) side becomes the positive pole, and a positive output voltage that gradually increases is obtained. t4~1. At the end of the period, switch S5 is turned on and the fifth stage electric IE is turned on.
When V5 becomes the input voltage, this human voltage is the reference voltage v
Since the voltage becomes higher than R, the current flows through the integrating capacitor (7) from the input side to the output side, and the integrating capacitor (4) is slightly discharged, resulting in an output as shown in waveform a2 in Figure 2. The voltage will drop slightly. Switch S6°Sy,
8st NAvc on vcsr), 11 pressure V6. V7.
V81ZII! Next, input the integrating capacitor (7
The discharge at point 1 gradually progresses, and finally returns to the potential at time to at the time of ts. Pseudo ωs@α3 is a sine wave of 906 or 14
It is symmetrical around Tokizuke. Pseudo ωs a (121 is a staircase wave, and by integrating this, a pseudo sine wave with good approximation can be obtained.

After time t8, the first switch S1 is turned on again, the first stage voltage vl lower than the reference voltage VR becomes the input voltage, and the generation of the next half-sine wave starts.

When changing the waveform Q2+ in the m2 diagram to a sine wave # wave, VC has the waveform (
The reference voltage vR may be subtracted from 121.

The pseudo sine wave formed by this circuit is used to form PWM pulses for inverter control.

Since the PWM pulse is formed by comparing a sine wave and a triangular wave, the multiplexer (2) is operated in synchronization with the triangular wave. When the frequency needs to be changed, the set feeding speed of the switches S, ~Ss connected to the multiplexer (2) is changed.

The amplitude of the sine wave is controlled by a level control circuit αD.

The invention is not limited to the embodiments described above.

It is deformable. For example, a buffer amplifier may be interposed before the input resistor (5). Also.

A circuit may be provided that switches the value of the input resistor (5) so that the amplitude of the output voltage waveform 0z is the same when the output frequency is 50 Hz and 60 Hz. Also, the reference voltage V
R may not be obtained using the voltage dividing resistor circuit of the resistors R1 to R9, but may be obtained using an independent voltage dividing circuit. -! Ta.

A staircase wave may be generated to obtain a sine wave from 06 to 360'.

〔Effect of the invention〕

As is clear from the above, according to the present invention, a pseudo sine wave can be obtained with a simple circuit configuration combining a single voltage dividing resistor circuit, a multiplexer, an operational amplifier, and an integrating capacitor.

[Brief explanation of drawings]

FIG. 2 is a circuit diagram showing an example VCgf of the present invention, an analogous sine wave generating circuit, and FIG. 2 is a voltage waveform diagram showing the states of each part of FIG. 1. (2)... Multiplexer, (4)... Operational amplifier, (51... Input resistance, (6)... Reference voltage supply line, (71... Integrating capacitor s I (I to R ，
···resistance.

Claims (1)

[Claims] (1) It has a plurality of divided voltage output lines for dividing and outputting the DC power supply voltage, and the voltage of the plurality of divided voltage output lines is adjusted so that a pseudo COS wave can be obtained at the output stage of the multiplexer described later. a voltage dividing resistor circuit having a set value, a multiplexer that sequentially selects and outputs the voltages of the plurality of divided voltage output lines so as to output a pseudo COS wave, and a voltage equal to the center voltage in the voltage dividing resistor circuit. a reference voltage supply line for supplying voltage; an operational amplifier having one input terminal connected to the multiplexer via an input resistor and the other input terminal connected to the reference voltage supply line; A pseudo sine wave generation circuit consisting of an integrating capacitor connected between one input terminal and an output terminal.