EP0851585A1 - Circuit for generating an electric signal of constant duration, said duration being independant of temperature and process variations - Google Patents
Circuit for generating an electric signal of constant duration, said duration being independant of temperature and process variations Download PDFInfo
- Publication number
- EP0851585A1 EP0851585A1 EP96830650A EP96830650A EP0851585A1 EP 0851585 A1 EP0851585 A1 EP 0851585A1 EP 96830650 A EP96830650 A EP 96830650A EP 96830650 A EP96830650 A EP 96830650A EP 0851585 A1 EP0851585 A1 EP 0851585A1
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- voltage
- circuit
- transistor
- terminal
- gate
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
Definitions
- the present invention relates to a circuit for the generation of an electrical signal of constant duration.
- the present invention relates to a circuit comprising a capacitor, a current generator to charge the capacitor with a constant current and a voltage comparator to compare the voltage present at the terminals of the capacitor with a reference voltage and supply at output a logical signal depending on the voltage at the terminals of the capacitor.
- the capacitor Upon power up of the circuit the capacitor is discharged and the output of the comparator holds a first logical level, e.g. of zero volt. Subsequently the current generator initiates charging of the capacitor and the voltage at its terminals increases until it reaches a threshold value of the comparator causing commutation of the output on a second logical level.
- a first logical level e.g. of zero volt.
- the capacitance of the capacitor and the value of the charge current determine the duration of the signal generated and consequently their accuracy affects the accuracy of the circuit.
- a known solution for generation of a constant current provides for the use of an appropriately biased MOS transistor.
- the transistor is caused to conduct a constant current between the source and drain terminals.
- ⁇ is the mobility of electrons
- C OX is the capacitance of the silicon oxide
- V gs is the gate biasing voltage
- V th is the threshold voltage of the MOS transistor.
- FIG 1 shows the current-voltage characteristics of an MOS transistor with three different temperatures T1, T2 and T3.
- the mobility of ⁇ varies very little with the process because it is one of the best-controlled parameters and, indeed, it depends mainly on the doping element and is known with an accuracy of less than 5%, the mobility can thus be considered dependent on temperature alone in a first approximation.
- the problem goes back to compensating the error introduced by the variation in the gate oxide thickness and the threshold voltage.
- FIG. 1 A known circuit diagram which permits providing an electrical signal by this method is shown in FIG 2.
- a capacitor C is connected between a ground reference voltage GND and a constant current generator consisting essentially of an MOS transistor M1 biased with a voltage V gsx between the gate and source terminals.
- the voltage present on the capacitor C is applied to a first input terminal of a voltage comparator COMP while a second input thereof is connected to a reference voltage V ref .
- the comparator COMP then compares the voltage at the terminals of the capacitor with the reference V ref and supplies at output a logical signal which is the result of the comparison.
- I D /C OX ratio is strongly dependent upon the threshold voltage of the transistor M1 since a variation of the threshold causes the transistor being no longer correctly biased. Consequently the I D /C OX ratio also varies with temperature.
- the technical problem underlying the present invention is to make available a circuit for the generation of an electrical signal of constant duration and independent of temperature and process variables to overcome the limitations indicated above with reference to the prior art.
- the solution idea underlying the present invention is to provided a circuit for the generation of an electrical signal of constant duration of the type comprising a capacitor, a constant current generator for charging the capacitor, and a voltage comparator to compare the voltage present at the terminals of the capacitor with a reference voltage and supply at output a digital signal dependent upon the voltage at the terminals of the capacitor, in which the current generator comprises a MOS transistor biased with a voltage V gsx between gate and source obtained as the difference between the sum of two gate-source voltages of two MOS transistors and a gate-source voltage of another MOS transistor.
- V gs V gsx
- V th is however a process variable which depends on the quantity of doping agent, the oxide thickness and the quality of the oxide-semiconductor interface, hence the relationship (1.3) can no longer be true with variation of the process parameters.
- a capacitor C is connected between a first terminal V cc of a supply voltage generator and a constant current generator consisting essentially of a first MOS transistor M1 and a reference biasing network 4.
- the transistor M1 has a gate terminal G connected to the biasing network 4, a drain terminal D connected, in a common node B, to a capacitor terminal C, and a source terminal S connected to a second terminal (GND) of the supply voltage generator, in particular a ground reference.
- a comparator COMP has a first input coupled to the node B and a second input connected to a reference voltage V ref .
- the voltage on the node B which depends on the charge status of the capacitor C, is compared by the comparator with the reference voltage V ref and a logical output signal OUT changes state when the voltage on the capacitor exceeds the reference voltage. In this manner the output signal OUT remains at a first logic level for a precise and well defined period of time to then switches to a second logic level.
- the biasing network 4 is made up of two distinct legs.
- a first leg comprises a second M2 and a third M3 transistor connected in diode configuration, i.e. each having its gate and source terminals joined to its drain terminal, and connected together in series between a current generator I1 and a reference voltage ⁇ V.
- a second leg comprises a fourth transistor M4 having a main source-drain conduction path connected in series with a current generator I 2 . Both legs are connected between the terminals V cc and GND of the power supply generator.
- the fourth transistor M4 has a gate terminal connected to the common node A between the current generator I1 and the drain terminal of the second transistor M2, a drain terminal connected to the power supply terminal V cc and a source terminal connected to the current generator I2 and to the gate terminal of the first transistor M1.
- the reference voltage ⁇ V is a voltage generator connected between the source terminal of the third transistor M3 and the terminal GND of the power supply generator.
- the idea is to obtain the threshold voltage V tho of the MOS transistor by subtracting from the sum of the V gs of the transistors M2 and M3, the V gs of the transistor M4 which must have an overdrive equal to the sum of the overdrives of the transistors M2 and M3. This result can be obtained as explained below by appropriately sizing the currents and transistors.
- ⁇ V ⁇ V 0 - ⁇ V th ⁇ T ⁇ ( T - 25)
- This circuit uses as current generator a current mirror 5 having a primary leg and a secondary leg.
- the voltage ⁇ V is provided as a voltage drop on a resistor R2 placed in series with the two transistors M2 and M3.
- the scheme for biasing the transistors M2, M3 and M4 shown in FIGS 3 and 4 is of course not the only one possible.
- the circuit shown in FIG 5 is an example thereof. This circuit differs from the circuit of FIG 3 only in the connection of the transistor M4. Indeed, the drain terminal of this transistor is connected to its own gate terminal in the common node A in which is applied the current of the generator I1. The important point is control of the biasing currents of the MOS transistors.
Abstract
A circuit for the generation of an electrical signal of
constant duration comprises a capacitor (C), a constant
current generator for charging said capacitor and a voltage
comparator (COMP) to compare the voltage present at the
terminals of the capacitor with a reference voltage (Vref)
and supply at output a digital signal (OUT) dependent upon
the voltage across the capacitor; the constant current
generator comprises a transistor (M1) biased with a voltage
(Vgsx) between gate and source obtained as the difference
between the sum of two gate-source voltages of two
transistors (M2,M3) and a gate-source voltage of another
transistor (M4).
Description
The present invention relates to a circuit for the
generation of an electrical signal of constant duration.
Specifically the present invention relates to a circuit
comprising a capacitor, a current generator to charge the
capacitor with a constant current and a voltage comparator
to compare the voltage present at the terminals of the
capacitor with a reference voltage and supply at output a
logical signal depending on the voltage at the terminals of
the capacitor.
Upon power up of the circuit the capacitor is discharged
and the output of the comparator holds a first logical
level, e.g. of zero volt. Subsequently the current
generator initiates charging of the capacitor and the
voltage at its terminals increases until it reaches a
threshold value of the comparator causing commutation of
the output on a second logical level.
The capacitance of the capacitor and the value of the
charge current determine the duration of the signal
generated and consequently their accuracy affects the
accuracy of the circuit.
A known solution for generation of a constant current
provides for the use of an appropriately biased MOS
transistor.
Indeed, by applying a biasing voltage between the gate and
source terminals the transistor is caused to conduct a
constant current between the source and drain terminals.
As known, there exists a biasing voltage Vgs = Vgsx of the
gate of an MOS transistor for which the drain current is
constant with temperature variation:
ID = µ · COX · (Vgs - Vth )2
Where µ is the mobility of electrons, COX is the
capacitance of the silicon oxide, Vgs is the gate biasing
voltage and Vth is the threshold voltage of the MOS
transistor.
This relationship can be readily deduced by observing the
drain current ID as a function of the Vgs with different
temperatures as illustrated in FIG 1 which shows the
current-voltage characteristics of an MOS transistor with
three different temperatures T1, T2 and T3.
As may be seen in that figure there is a point on the chart
corresponding to a voltage Vgsx at which the three curves
intersect. This relationship leads to the assumption that
by using this current to charge a capacitor there could be
provided an electrical signal of constant duration with
temperature change of the device.
In reality the problem is not so simple since COX, Vth and
µ vary with the process in addition to varying with the
temperature.
The mobility of µ varies very little with the process
because it is one of the best-controlled parameters and,
indeed, it depends mainly on the doping element and is
known with an accuracy of less than 5%, the mobility can
thus be considered dependent on temperature alone in a
first approximation.
The problem goes back to compensating the error introduced
by the variation in the gate oxide thickness and the
threshold voltage.
The prior art eliminates dependence on COX by using as
capacitance a capacitor whose dielectric is the same gate
oxide used in the transistors. In this manner the
relationship between MOS current and capacitance becomes:
ID C = ID K 1 · COX = µ · COX · (Vgsx - Vth )2 K 1 · COX = µ · (Vgsx - Vth )2 K 1
where K1 is a constant area factor.
A known circuit diagram which permits providing an
electrical signal by this method is shown in FIG 2.
In FIG 2 a capacitor C is connected between a ground
reference voltage GND and a constant current generator
consisting essentially of an MOS transistor M1 biased with
a voltage Vgsx between the gate and source terminals. The
voltage present on the capacitor C is applied to a first
input terminal of a voltage comparator COMP while a second
input thereof is connected to a reference voltage Vref. The
comparator COMP then compares the voltage at the terminals
of the capacitor with the reference Vref and supplies at
output a logical signal which is the result of the
comparison.
One disadvantage of this circuit is that the ID/COX ratio
is strongly dependent upon the threshold voltage of the
transistor M1 since a variation of the threshold causes the
transistor being no longer correctly biased. Consequently
the ID/COX ratio also varies with temperature.
The technical problem underlying the present invention is
to make available a circuit for the generation of an
electrical signal of constant duration and independent of
temperature and process variables to overcome the
limitations indicated above with reference to the prior
art.
The technical problem is solved by a circuit of the type
indicated above and defined in the characterizing part of
claims 1 to 6.
The solution idea underlying the present invention is to
provided a circuit for the generation of an electrical
signal of constant duration of the type comprising a
capacitor, a constant current generator for charging the
capacitor, and a voltage comparator to compare the voltage
present at the terminals of the capacitor with a reference
voltage and supply at output a digital signal dependent
upon the voltage at the terminals of the capacitor, in
which the current generator comprises a MOS transistor
biased with a voltage Vgsx between gate and source obtained
as the difference between the sum of two gate-source
voltages of two MOS transistors and a gate-source voltage
of another MOS transistor.
The characteristics and advantages of the method in
accordance with the present invention are set forth in the
description of an embodiment thereof given below by way of
non-limiting example with reference to the annexed
drawings.
Assuming that the specific capacitance of the gate oxide
COX be constant with temperature variation, from the
relationship (1.1) on the drain current of the MOS
transistor it can be deducted that there is a gate voltage
Vgs = Vgsx such that:
ID COX = µ · (Vgsx - Vth )2 = Cost
where mobility varies with the temperature proportionately
to a factor
T T 0 -32 ,
while the threshold voltage Vth varies with the temperature
in such a manner as to compensate the mobility variations.
Vth is however a process variable which depends on the
quantity of doping agent, the oxide thickness and the
quality of the oxide-semiconductor interface, hence the
relationship (1.3) can no longer be true with variation of
the process parameters.
To keep this relationship valid it is necessary to bias the
MOS with a Vgsx dependent upon the process variables.
Let us consider
Vgsx = ΔV 0 + Vth 0
as the biasing voltage,
where Vtho is the threshold voltage of the process at ambient temperature 25°C and ΔVo is a constant voltage and Vth = Vth 0 + ΔVth ΔT · (T - 25)
where ΔVth/ΔT is the variation of the threshold with
temperature.
where Vtho is the threshold voltage of the process at ambient temperature 25°C and ΔVo is a constant voltage and
Substituting both the expressions in (1.3) we find:
ID COX = µ · ΔV 0 + Vth 0 - Vth 0 - ΔVth ΔT · (T - 25) 2 = Cost
from which is extracted:
ID COX = µ · ΔV 0 - ΔVth ΔT · (T - 25) 2 = Cost
In this last relationship dependence on the threshold
voltage has been eliminated. There appear only two values
ΔVo and (ΔVth/ΔT) which are independent of the process
variables.
The present invention consists of the electrical circuit
which provides this last compensation by biasing the gate
of the MOS transistor with a voltage Vgsx =ΔVo +Vtho which
makes the ID/COX ratio independent of the threshold voltage
and temperature variations.
A circuit in which this compensation is implemented is
shown in detail in FIG 3.
A capacitor C is connected between a first terminal Vcc of
a supply voltage generator and a constant current generator
consisting essentially of a first MOS transistor M1 and a
reference biasing network 4.
The transistor M1 has a gate terminal G connected to the
biasing network 4, a drain terminal D connected, in a
common node B, to a capacitor terminal C, and a source
terminal S connected to a second terminal (GND) of the
supply voltage generator, in particular a ground reference.
A comparator COMP has a first input coupled to the node B
and a second input connected to a reference voltage Vref.
The voltage on the node B, which depends on the charge
status of the capacitor C, is compared by the comparator
with the reference voltage Vref and a logical output signal
OUT changes state when the voltage on the capacitor exceeds
the reference voltage. In this manner the output signal OUT
remains at a first logic level for a precise and well
defined period of time to then switches to a second logic
level.
The biasing network 4 is made up of two distinct legs. A
first leg comprises a second M2 and a third M3 transistor
connected in diode configuration, i.e. each having its gate
and source terminals joined to its drain terminal, and
connected together in series between a current generator I1
and a reference voltage ΔV.
A second leg comprises a fourth transistor M4 having a main
source-drain conduction path connected in series with a
current generator I2. Both legs are connected between the
terminals Vcc and GND of the power supply generator.
The fourth transistor M4 has a gate terminal connected to
the common node A between the current generator I1 and the
drain terminal of the second transistor M2, a drain
terminal connected to the power supply terminal Vcc and a
source terminal connected to the current generator I2 and
to the gate terminal of the first transistor M1.
The reference voltage ΔV is a voltage generator connected
between the source terminal of the third transistor M3 and
the terminal GND of the power supply generator.
The idea is to obtain the threshold voltage Vtho of the MOS
transistor by subtracting from the sum of the Vgs of the
transistors M2 and M3, the Vgs of the transistor M4 which
must have an overdrive equal to the sum of the overdrives
of the transistors M2 and M3. This result can be obtained
as explained below by appropriately sizing the currents and
transistors.
With reference to FIG 3 we have:
Vgsx = ΔV + Vgs 2 + Vgs 3 - Vgs 4
if we consider that:
Vgs = Vth + overdrive = Vth + L · ID 2 · µ · COX · W
where L and W are the physical dimensions of the transistor
and substituting this expression in the previous equation
(1.5) we have:
Vgsx = ΔV + Vth + L 2 · I 1 2 · µ · COX · W 2 + L 3 · I 1 2 · µ · COX · W 3 +
- L 4 · I 2 2 · µ · COX · W 4
In order that the overdrives compensate each other there
must be:
L 2 · I 1 2 · µ · COX · W 2 + L 3 · I 1 2 · µ · COX · W 3
- L 4 · I 2 2 · µ · COX · W 4
(1.7) is considerably simplified if
L 2 W 2 = L 3 W 3
and in this case it is reduced to:
4 · I 1 · L 2 W 2 = I 2 · L 4 W 4
This allows finding a biasing voltage Vgsx =ΔV+Vth in which
however Vth varies with temperature. It is therefore
necessary to arrange that ΔV compensate this variation:
V gsx = ΔV + Vth = ΔV + Vth 0 + ΔVth ΔT · (T - 25) = ΔV 0 + Vth0
For this last equality be true, ΔV must be:
ΔV = ΔV 0 - ΔVth ΔT · (T - 25)
An example of application in which this voltage is provided
is the circuit shown in FIG 4. This circuit uses as current
generator a current mirror 5 having a primary leg and a
secondary leg.
In the primary leg a current I is forced through a bipolar
transistor T biased with a current Vbias and placed in
series with a resistor R1 while in the secondary leg flows
a current I1 =α·I equal to α times the current I.
The voltage ΔV is provided as a voltage drop on a resistor
R2 placed in series with the two transistors M2 and M3.
From the same circuit can be taken the behaviour of ΔV with
temperature variation:
ΔV = α · I · R 2 = α · R 2 · Vbias - Vbe 0 - ΔVbe ΔT · (T - 25) R 1
from which is found:
ΔV = α · R 2 R 1 · (Vbias - Vbe 0 ) - α · R 2 R 1 · ΔVbe ΔT · (T - 25)
From this and from (1.9) it is deduced that:
ΔV 0 = α · R 2 R 1 · (Vbias - Vbe 0 )
and that
ΔVth ΔT = α · R 2 R 1 · ΔVbe ΔT
Setting two parameters, e.g. α and R1, it is possible to
find the other two, the value of the resistor R2 and the
biasing voltage of the transistor Vbias.
The scheme for biasing the transistors M2, M3 and M4 shown
in FIGS 3 and 4 is of course not the only one possible. The
circuit shown in FIG 5 is an example thereof. This circuit
differs from the circuit of FIG 3 only in the connection of
the transistor M4. Indeed, the drain terminal of this
transistor is connected to its own gate terminal in the
common node A in which is applied the current of the
generator I1. The important point is control of the biasing
currents of the MOS transistors.
Claims (6)
- Circuit for the generation of an electrical signal of constant duration and independent of temperature and process variables of the type comprising a capacitor (C), a constant current generator for charging the capacitor and a voltage comparator (COMP) to compare the voltage present across the capacitor with a reference voltage (Vref) and supply at output a digital signal (OUT) dependent upon the voltage across the capacitor (C) with said constant current generator comprising a first MOS transistor (M1) having a gate terminal, a source terminal and a drain terminal, biased with a fixed voltage (Vgsx) between gate and source to conduct a certain current between drain and source and characterized in that said fixed voltaged is obtained as the difference between the sum of two gate-source voltages (Vgs2 e Vgs3) of a second (M2) and a third (M3) MOS transistors and a gate-source voltage (Vgs4) of a fourth MOS transistor (M4) .
- Circuit in accordance with claim 1 and characterized in that said second (M2) and third (M3) transistors are connected in diode configuration with each having its gate terminal joined to its drain terminal and are connected together in series between a first current generator (I1) and a reference voltage (ΔV).
- Circuit in accordance with claim 2 and characterized in that the fourth transistor (M4) has a gate terminal connected to the common node (A) between the first current generator (I1) and the drain terminal of the second transistor (M2) with a drain terminal connected to a power supply terminal (Vcc) and a source terminal connected to a second current generator (I2) and to the gate terminal of the first transistor (M1) .
- Circuit in accordance with claim 2 and characterized in that the reference voltage (ΔV) is a voltage generator connected between the source terminal of the third transistor (M3) and a ground reference voltage (GND).
- Circuit in accordance with claim 4 and characterized in that the voltage generator is provided by means of a resistor (R2) connected between the source terminal of the third transistor (M3) and a ground reference voltage (GND).
- Circuit in accordance with claim 5 and characterized in that the first current generator (I1) is a secondary leg of a current mirror (5) in which flows a current (α·I) directly proportionate to the current (I) running in the primary leg of the same current mirror (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP96830650A EP0851585A1 (en) | 1996-12-24 | 1996-12-24 | Circuit for generating an electric signal of constant duration, said duration being independant of temperature and process variations |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP96830650A EP0851585A1 (en) | 1996-12-24 | 1996-12-24 | Circuit for generating an electric signal of constant duration, said duration being independant of temperature and process variations |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP0851585A1 true EP0851585A1 (en) | 1998-07-01 |
Family
ID=8226093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP96830650A Pending EP0851585A1 (en) | 1996-12-24 | 1996-12-24 | Circuit for generating an electric signal of constant duration, said duration being independant of temperature and process variations |
Country Status (1)
| Country | Link |
|---|---|
| EP (1) | EP0851585A1 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4119869A (en) * | 1976-02-26 | 1978-10-10 | Tokyo Shibaura Electric Company, Ltd. | Constant current circuit |
| US4199693A (en) * | 1978-02-07 | 1980-04-22 | Burroughs Corporation | Compensated MOS timing network |
| GB2071955A (en) * | 1980-03-17 | 1981-09-23 | Philips Nv | Field-effect transistor current stabilizer |
| JPS60113521A (en) * | 1983-11-24 | 1985-06-20 | Fujitsu Ltd | Timing circuit |
| US4642552A (en) * | 1985-03-04 | 1987-02-10 | Hitachi, Ltd. | Stabilized current source circuit |
| EP0565806A1 (en) * | 1992-04-16 | 1993-10-20 | STMicroelectronics S.r.l. | Accurate MOS threshold voltage generator |
-
1996
- 1996-12-24 EP EP96830650A patent/EP0851585A1/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4119869A (en) * | 1976-02-26 | 1978-10-10 | Tokyo Shibaura Electric Company, Ltd. | Constant current circuit |
| US4199693A (en) * | 1978-02-07 | 1980-04-22 | Burroughs Corporation | Compensated MOS timing network |
| GB2071955A (en) * | 1980-03-17 | 1981-09-23 | Philips Nv | Field-effect transistor current stabilizer |
| JPS60113521A (en) * | 1983-11-24 | 1985-06-20 | Fujitsu Ltd | Timing circuit |
| US4642552A (en) * | 1985-03-04 | 1987-02-10 | Hitachi, Ltd. | Stabilized current source circuit |
| EP0565806A1 (en) * | 1992-04-16 | 1993-10-20 | STMicroelectronics S.r.l. | Accurate MOS threshold voltage generator |
Non-Patent Citations (2)
| Title |
|---|
| "DELAYED POWER-ON CIRCUIT WITH SOFT START", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 35, no. 7, 1 December 1992 (1992-12-01), pages 197 - 198, XP000332979 * |
| PATENT ABSTRACTS OF JAPAN vol. 009, no. 266 (E - 352) 23 October 1985 (1985-10-23) * |
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