JPH0644704B2 - Differential comparator circuit with hysteresis - Google Patents

Description

The present invention relates to a differential comparator circuit with hysteresis suitable for a digital magnetic reproducing device.

[Prior Art] A conventional reproducing apparatus for recording and reproducing a digital signal using a magnetic tape is constructed as shown in FIG. In FIG. 7, a reproducing head 2 in contact with the magnetic recording medium 1 reproduces a digital signal recorded in the recording medium 1 in a binary format. At the output stage of the reproducing head 2, a preamplifier 3, an attenuator 4 for level adjustment, an amplifier 5,
A low pass filter 6 for removing unnecessary high frequency components,
A differential circuit 7 for detecting the peak of the reproduced signal, a differential comparator circuit 8 with hysteresis for waveform shaping, and a D-type flip-flop 9 for data output are sequentially provided, and a clock signal of the D flip-flop 9 is supplied. In order to obtain, a zero cross detection circuit 10 and a bidirectional mono-multivibrator 11 are provided between the differentiating circuit 7 and the clock input terminal C.
And are provided.

The differentiating circuit 7 is for differentiating the reproduction signal so that a zero cross is generated corresponding to the peak of the magnetic reproduction signal obtained from the head 2, and the capacitor 12 and the resistor 13 are provided.
It includes a time constant circuit composed of, an amplifier circuit 14, and an offset voltage removing variable resistor 15. In addition, since the differential comparator circuit 8 is provided in the subsequent stage, the differentiating circuit 7 is configured to send out a pair of outputs having mutually opposite phases to the first and second transmission lines 16 and 17. The first signal on the first transmission line 16 and the second signal on the second transmission line 17 have substantially the same amplitude and a phase difference of 180 degrees. The variable resistor 15 is adjusted so that the sum of the first signal and the second signal is zero, that is, the offset voltage is zero.

The hysteresis-equipped differential comparator circuit 8 includes a voltage comparator 18 including an operational amplifier, a first input resistor 19 connected between the non-inverting input terminal and the first transmission line 16, an inverting input terminal and a first input resistor 19. The second input resistor 20 connected between the second transmission line 17 and the feedback resistor 21.
And a resistor 22 connected between the output terminal and the power supply terminal indicated by Vcc, a resistor 23 connected between the inverting input terminal and ground (zero volt), and between the inverting input terminal and the Vcc power supply terminal. And a resistor 24 connected to.

The zero-cross detection circuit 10 includes a voltage comparator 25, one input resistor 26 connected between the non-inverting input terminal and the first transmission line 16, and an inverting input terminal and the second transmission line 17. The other input resistor 27 connected
And a resistor 2 connected between the output terminal and the Vcc power supply terminal.
8 and.

FIG. 8 shows the voltage waveform of each part in FIG. Fig. 8 (A)
The first and second signals A1 and A2 of the first and second transmission lines 16 and 17 shown in FIG. 3 are not compared as they are by the comparator 18, but are compared with the waveform shown in FIG. That is, the input signal B1 is input to the non-inverting input terminal and the input signal B2 is input to the inverting input terminal, and comparison is performed so as to have hysteresis, and the comparison output shown in FIG. 8C is obtained. The hysteresis is generated by feeding back the output of the comparator 18 to the non-inverting input terminal with the resistor 21.

In the zero-crossing detection circuit 10, the first and second signals A shown in FIG.
1 and A2 are compared as they are, and as shown in FIG. 8 (A), a rectangular wave output whose state changes at the time of intersection (zero crossing) is obtained.

The bidirectional monomultivibrator 11 responds to both the leading edge and the trailing edge of the pulse shown in FIG. 8 (D) to generate a negative pulse having a time width T shown in FIG. 8 (E). The D flip-flop 9 uses the leading edge of the positive pulse as the clock signal at the time when the pulse of FIG.
The data of FIG. 8C is read, and the read data of FIG. 8F is output from the Q output terminal. As a result, the read data can be read into the D flip-flop 9 at a time point having a certain time relationship with the zero-cross time point and output.

As described above, when the differential comparator circuit 8 has hysteresis, the differential comparator does not respond to noise within the range of the hysteresis value, so that accurate data detection is possible.

[Problems to be Solved by the Invention] However, the conventional circuit of FIG. 8 has the following problems.

(1) Since the differential circuit 7 and the differential comparator circuit 8 are DC-coupled, the DC offset voltage in the differential circuit 7 affects the hysteresis of the differential comparator circuit 8. Therefore, the offset voltage of the differentiation circuit 7 is set to the variable resistance 1
It had to be adjusted to zero by 5, and the adjustment of the reproducing circuit was troublesome.

(2) Resistor 1 when changing the value of hysteresis
The values of 9 and 20 had to be changed in conjunction with each other, and adjustment of the hysteresis value was troublesome.

Therefore, an object of the present invention is to provide a differential comparator circuit which can be AC-coupled so as not to be affected by the offset voltage of the circuit at the preceding stage and whose hysteresis can be easily adjusted.

[Means for Solving the Problems] The present invention for solving the above problems and achieving the above objects includes a first signal and an amplitude substantially the same as that of the first signal. A circuit for comparing the first signal with a second signal having a phase difference of substantially 180 degrees with hysteresis, wherein a non-inverting input terminal is coupled to a transmission line of the first signal. A first comparator having an inverting input terminal coupled to the second signal transmission line, a non-inverting input terminal coupled to the second signal transmission line, and an inverting input terminal coupled to the first signal A second comparator coupled to the transmission line; a first bias voltage applying means for applying a first bias voltage to a non-inverting input terminal of the first comparator; and an inverting input terminal of the first comparator for the first bias voltage applying means. Different from the first bias voltage Second bias voltage applying means for applying a second bias voltage;
Third bias voltage applying means for applying a bias voltage substantially the same as the first bias voltage to the non-inverting input terminal of the comparator, and the second bias voltage to the inverting input terminal of the second comparator. Fourth bias voltage applying means for applying a bias voltage substantially the same as
Set in response to the conversion of the first comparator from the first output state to the second output state, and in response to the conversion of the second comparator from the first output state to the second output state. The present invention relates to a differential comparator circuit with hysteresis composed of a flip-flop circuit that is reset by the following.

[Operation] When the first and second bias voltages V1 and V2 having different values are applied to the non-inverting input terminal and the inverting input terminal of the first comparator of the above invention, these bias voltages V1 and V2 are applied. Centered on the intermediate value of (V1 -V2) / 2
The two input signals become symmetrical and the intersection of the two input signals occurs on the median value. As a result, the positive-phase and negative-phase noise components biased by the first and second bias voltages V1 and V2 do not cross each other unless their amplitude is (V1 -V2) / 2 or more. Therefore, a comparison operation having hysteresis or a threshold value is performed, and noise removal is achieved.

[Embodiment] Next, a reproducing circuit of a digital magnetic tape device according to an embodiment of the present invention will be described with reference to FIGS. However, in FIG. 1, reference numerals 1 to 6, 9, 12, and 1
The components denoted by 3, 14, 16, and 17 are substantially the same as those designated by the same reference numerals in FIG. 8, and therefore their description is omitted.

The differential differential comparator circuit 8a with hysteresis coupled to the first and second transmission lines 16 and 17 includes first and second comparators 31 and 32 which are open collector output type operational amplifiers. The non-inverting input terminal 33 of the first comparator 31 is AC-coupled to the first transmission line 16 via the first coupling capacitor C1.
The inverting input terminal 34 is AC coupled to the second transmission line 17 via a second coupling capacitor C2. On the other hand, the non-inverting input terminal 35 of the second comparator 32 is connected to the AC of the second transmission line 17 via the third coupling capacitor C3.
And the inverting input terminal 36 is coupled to the fourth coupling capacitor C
AC coupled to the first transmission line 16 via 4. The non-inverting input terminal 33 of the first comparator 31 is connected to the first voltage source terminal 38 via the first bias resistor R1 and the potentiometer 37, and the inverting input terminal 3
4 is connected to the second voltage source terminal 39 via the second bias resistor R2, the inverting input terminal 35 of the second comparator 32 is connected to the potentiometer 37 via the third bias resistor R3, The inverting input terminal 36 is connected to the second voltage source terminal 39 via the fourth Baice resistor R4. In this embodiment, the first voltage source terminal 38 is connected to a 12 volt DC power supply (not shown) and the second voltage source terminal 39 is connected to a 6 volt DC power supply (not shown). . The bias voltages are separated from each other by coupling capacitors C1 to C4.

The output terminal of the first comparator 31 is connected to the set terminal 41 of the set / reset flip-flop 40, and the output terminal of the second comparator 32 is connected to the reset terminal 42 of the flip-flop 40. The output terminals of the first and second comparators 31 and 32 are the fifth terminals.
Also, it is connected to the power supply terminal Vcc through the sixth resistors R5 and R6.

The flip-flop 40 has two NAND gates 43, 4
4 is a well-known circuit, which has a positive output terminal 4
5 and outputs a comparison output with hysteresis from this output terminal 45. The output terminal 45 is D as in the case of FIG.
It is connected to the data input terminal D of the flip-flop 9.

A zero-cross detection circuit 10a having a function similar to that of the zero-cross detection circuit 10 shown in FIG. 7 is connected to the first and second transmission lines 16 and 17, and a mono-multivibrator circuit 11a is provided at this output stage. The terminal is connected to the clock terminal C of the D flip-flop 9.

FIG. 2 shows in detail the zero-cross detection circuit 10a and the mono-multivibrator circuit 11a shown in FIG. The zero-cross detection circuit 10a includes a pair of comparators 46 and 47,
A pair of OR-type NANs forming a flip-flop
D gates 48, 49 and a pair of AND type NANDs
It has gates 50 and 51. The pair of input terminals of the first and second comparators 46 and 47 is the coupling capacitor 5
First and second transmission lines 16, 17 via 2, 53
Are AC-coupled to the resistors 54 and 55, respectively.
It is connected to the DC bias power supply terminal 56 via.
The output terminal of one comparator 46 is the NAND gate 4
8 is connected to one input terminal and the other comparator 4
The output terminal of 7 is connected to one input terminal of the NAND gate 49. The output terminal of one NAND gate 48 is connected to the input terminal of the other NAND gate 49 to form a flip-flop, and the resistance 57
And a capacitor 58 and a delay circuit,
Connected to one input terminal of the AND gate 50, and further N
It is directly connected to one input terminal of the AND gate 51. The output terminal of the other NAND gate 49 is connected to the input terminal of the NAND gate 48 to form a flip-flop, and the NAND gate 51 of the next stage is connected via a delay circuit composed of a resistor 59 and a capacitor 60. It is connected to the input terminal and is also directly connected to the input terminal of the other NAND gate 50. Two N
The outputs of the AND gates 50 and 51 are connected to the mono multivibrator circuit 11a.

[Operation] For convenience of explanation, the third transmission line 16 at the output stage of the differentiating circuit 7a shown in FIG.
When the first signal A1 shown in FIG. 7A is obtained and the second signal A2 having the same amplitude as the first signal A1 but having a phase difference of 180 degrees is obtained on the second transmission line 17. If so, the AC component of each signal A1 and A2 will be the coupling capacitor C
It inputs to each input terminal 33-36 of the 1st and 2nd comparators 31 and 32 via 1, C2, C3, and C4. Here, the fact that the first signal A1 is input to the non-inverting input terminal 33 for the first comparator 31 and to the inverting input terminal 34 for the second comparator 32 means that there is a hysteresis characteristic. It is important to get.

The first through the first to fourth coupling capacitors C1 to C4
And the second signal is the first to fourth bias resistors R1 to R.
1 with a DC bias voltage applied via
And the respective inputs of the second comparators 31 and 32. The non-inverting input terminal 33 of the first comparator 31 is connected to the third voltage source terminal 38 via the potentiometer 37.
The first bias voltage V1 shown in FIG. 3B is applied to the inverting input terminal 34 from the second voltage source terminal 39, which is slightly lower than the first bias voltage V shown in FIG. 3B.
Bias voltage V2 is applied. As a result, the first signal A1 in FIG. 3 (A) is biased by the first bias voltage V1 to become the first input signal B1 in FIG. 3 (B), and the non-inverting input of the first comparator 31. Inputted to the terminal 33, the second signal A2 is biased by the second bias voltage V2 to become the second input signal B2 of FIG. 3 (B),
Input to the inverting input terminal 34. As a result, the intersection of the first input signal B1 and the second input signal B2 occurs at an intermediate voltage V0 in the region between the first bias voltage V1 and the second bias voltage V2. The first comparator 31 is
As shown in FIG. 3C, a high level output is generated when the first input signal B1 is higher than the second input signal B2, and a low level output is generated when it is low.

Even if noise is input instead of the first and second signals A1 and A2 shown in FIG. 3A, this noise also passes through the coupling capacitors C1 and C2, and then the first and second bias voltages V1 and Since it is biased with V2, if the noise level is lower than (V1-V2) / 2, the noise biased with the first bias voltage V1 and the anti-phase noise biased with the second bias voltage V2 are Do not cross. As a result, the comparator 31 does not respond to noise. Although the case where only noise is input alone has been described above, the effect of noise removal also occurs when noise is superimposed on the first and second signals A1 and A2. Therefore, the first
Of the comparator 31 functions similarly to a comparator having a hysteresis voltage Vh of (V1 -V2) / 2.

The non-inverting input terminal 35 of the second comparator 32 has a second
The third input signal B3 in FIG. 3B, which is the signal A2 of FIG. 3 biased by the first bias voltage V1, is input, and the inverting input terminal 36 receives the first signal A1 of the second bias voltage. A fourth input signal B4, which is biased with voltage V2, is input. As a result, the first bias voltage V1
The intermediate voltage V0 between the second bias voltage V2 and the second bias voltage V2 causes the intersection of the third and fourth input signals B3 and B4, and FIG.
The voltage comparison output shown in is obtained. In the second comparator 32 as well as the first comparator 32 (V
A hysteresis voltage of 1-V2) / 2 is obtained, and it does not respond to noise lower than this hysteresis voltage.

The pair of zero-cross comparators 46 and 47 of the zero-cross detection circuit 10a shown in FIG. 2 have no hysteresis in order to accurately obtain time-axis information, and the first and second signals A1 shown in FIG. , A2 are compared. The voltage comparison by the pair of zero-cross comparators 46 and 47 and the operation of the flip-flop composed of the pair of NAND gates 48 and 49 have no hysteresis, and the first and second comparators 31 and 32 of FIG. It is the same as the flip-flop 40. The delay circuit composed of the resistor 57 and the capacitor 58 and the NAND gate 50 are shown in FIG.
Form a narrow negative pulse. Similarly, the delay circuit including the resistor 59 and the capacitor 60 and the NAND gate 51 form the narrow negative pulse shown in FIG. 4C. The mono-multivibrator circuit 11a is triggered in synchronization with the transition from the high level to the low level in FIGS.
The negative pulse shown in FIG. The width of the negative pulse is set to be slightly shorter than the zero-cross mutual interval (bit width). The pulse shown in FIG. 4 (D) is input as a clock pulse to the clock terminal C of the D flip-flop 9 shown in FIG. 1, and the data shown in FIG. 3 (E) is synchronized with the rising from this low level to the high level. The data of the input terminal D is read.

This embodiment has the following advantages.

(1) First and second comparators 31 and 32 are coupled to the first and second comparators 31 and 32 via coupling capacitors C1, C2, C3 and C4.
Since the signals A1 and A2 are input, the influence of the DC component of the first and second signals A1 and A2, that is, the offset voltage of the differentiating circuit 7a at the preceding stage is eliminated. As a result, it becomes unnecessary to adjust the offset voltage to zero in the differentiating circuit 7a, which facilitates the circuit adjustment.

(1) The hysteresis value is the first and second bias voltage V1
, V2, it is possible to easily set a desired hysteresis value.

(3) Since the zero-cross detection circuit 10a also includes two AC-coupled comparators 46 and 47, it is possible to detect zero-cross without the influence of the offset voltage.

[Modification] The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example.

(1) The second bias voltage source terminal 39 as shown in FIG.
A potentiometer 39a is connected between the second and fourth bias resistors R2 and R4 and the second bias voltage V2
May be adjusted. Further, both the first and second bias voltages V1 and V2 may be adjustable.

(2) First and second comparators 3 as shown in FIG.
The trigger circuit 6 is provided between the flip-flop 40 and the flip-flop 40.
It is also possible to connect 1 and 62 and form a trigger pulse to give a set pulse and a reset pulse to the flip-flop 40.

(3) Connect one ends of the first and third bias resistors R1 and R3 in common as shown in FIG. 1, and also connect one ends of the second and fourth bias resistors R2 and R4 in common. Although it is convenient for simplifying the circuit configuration, an independent voltage source may be connected to the first to fourth bias resistors R1 to R4 as necessary. Further, the first and second bias voltages may be obtained from two voltage dividing points in a common voltage dividing circuit.

(4) The present invention is not limited to the case where the read data is obtained from the reproduction signal, but can be applied to various signal detection similar to this.

EFFECTS OF THE INVENTION As is apparent from the above, according to the present invention, a desired hysteresis value can be easily obtained in the differential comparator circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a magnetic reproducing circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing in detail the zero-cross detection circuit 10a of FIG. 1, and FIG. 3 is a voltage waveform diagram of each part of FIG. 4, FIG. 4 is a voltage waveform diagram of each part of FIG. 2, FIG. 5 is a circuit diagram showing a circuit for applying a second bias voltage of a modified example, and FIG. 6 is a part of a differential comparator of the modified example. Circuit diagram, FIG. 7 is a circuit diagram showing a conventional magnetic reproducing circuit, and FIG. 8 is a voltage waveform diagram of each part of FIG. 7a ... differential circuit, 8a ... differential comparator circuit with hysteresis, 9 ... D flip-flop, 31 ... first
Comparator, 32 ... Second comparator, 38 ...
... first voltage source terminal, 39 ... second voltage source terminal, 40
……flip flop.

Claims (4)

[Claims] 1. A first signal having substantially the same amplitude as the first signal and substantially 180 degrees from the first signal.
A circuit for comparing with a second signal having a phase difference of 10 degrees with hysteresis, wherein a non-inverting input terminal is coupled to a transmission line of the first signal, and an inverting input terminal is connected to the second signal. A first comparator coupled to said transmission line, and a second comparator having a non-inverting input terminal coupled to said second signal transmission line and an inverting input terminal coupled to said first signal transmission line A first bias voltage applying means for applying a first bias voltage to the non-inverting input terminal of the first comparator; and a second bias voltage different from the first bias voltage for the inverting input terminal of the first comparator. Second bias voltage applying means for applying a bias voltage, and a third via for applying a bias voltage substantially the same as the first bias voltage to the non-inverting input terminal of the second comparator. Voltage applying means, fourth bias voltage applying means for applying to the inverting input terminal of the second comparator a bias voltage that is substantially the same as the second bias voltage, and first bias voltage of the first comparator. A flip-flop circuit which is set in response to the conversion from the output state to the second output state and is reset in response to the conversion from the first output state to the second output state of the second comparator, Comprising a differential comparator circuit with hysteresis. 2. The first bias voltage applying means is the first bias voltage applying means.
And a first bias resistor connected between the first voltage source and the non-inverting input terminal of the first comparator, and the second bias voltage applying means is a second bias voltage applying means. And a second bias resistor connected between the second voltage source and the inverting input terminal of the first comparator, and the third bias voltage applying means includes the first bias voltage applying means. And a third bias resistor connected between the non-inverting input terminal of the second comparator and the fourth bias voltage applying means, wherein the fourth bias voltage applying means includes the second voltage source and the second voltage source. The differential comparator circuit with hysteresis according to claim 1, comprising a fourth biasing resistor connected between the comparator and the inverting input terminal. 3. The differential comparator circuit with hysteresis according to claim 2, wherein the first voltage source is a voltage adjustable power source. 4. The differential comparator circuit with hysteresis according to claim 2, wherein the second voltage source is a voltage adjustable power source.