JPS6125057Y2 - - Google Patents

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Publication number
JPS6125057Y2
JPS6125057Y2 JP11903177U JP11903177U JPS6125057Y2 JP S6125057 Y2 JPS6125057 Y2 JP S6125057Y2 JP 11903177 U JP11903177 U JP 11903177U JP 11903177 U JP11903177 U JP 11903177U JP S6125057 Y2 JPS6125057 Y2 JP S6125057Y2
Authority
JP
Japan
Prior art keywords
circuit
amplifier
detection circuit
waveform
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11903177U
Other languages
Japanese (ja)
Other versions
JPS5446315U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11903177U priority Critical patent/JPS6125057Y2/ja
Publication of JPS5446315U publication Critical patent/JPS5446315U/ja
Application granted granted Critical
Publication of JPS6125057Y2 publication Critical patent/JPS6125057Y2/ja
Expired legal-status Critical Current

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  • Digital Magnetic Recording (AREA)
  • Manipulation Of Pulses (AREA)

Description

【考案の詳細な説明】 本考案は磁気記録再生装置等に使用される磁気
再生回路に関するものである。
[Detailed Description of the Invention] The present invention relates to a magnetic reproducing circuit used in a magnetic recording/reproducing device or the like.

磁気再生回路としては従来、磁気ヘツド等から
の情報信号のピーク値ごとに出力を反転して情報
信号のデイジタル化を行なういわゆるピーク検出
方式や、磁気ヘツド等からの情報信号が一定基準
値に達するごとに出力を反転して情報信号のデイ
ジタル化を行なういわゆるレベル検出方式等が使
用されていた、しかしピーク検出方式は入力のピ
ーク値ごとに出力を出すためノイズに対して誤動
作しやすく、又レベル検出方式では入力の一定レ
ベル値ごとに出力を出すため、磁気カード等の記
録媒体の走行スピードに変動が生じて磁気ヘツド
の出力レベルが変動した時等に誤動作しやすくな
る等両方式共互いに欠点を有していた。
Conventionally, magnetic reproducing circuits have used the so-called peak detection method, which digitizes the information signal by inverting the output at each peak value of the information signal from the magnetic head, etc., or the so-called peak detection method, in which the information signal from the magnetic head, etc. reaches a certain reference value. The so-called level detection method was used to digitize the information signal by inverting the output at each input peak value.However, the peak detection method outputs an output at each input peak value, so it is prone to malfunction due to noise, and the level detection method Since the detection method outputs an output for each fixed level value of the input, both methods have their own drawbacks, such as the possibility of malfunctions when the output level of the magnetic head changes due to fluctuations in the running speed of the recording medium such as a magnetic card. It had

本考案はこの様な欠点を除去し、ノイズの影響
を受けにくく、記録媒体の走行スピードの変化に
対しても安定した動作を行なう磁気再生回路を提
供しようとするものである。
The present invention aims to eliminate these drawbacks and provide a magnetic reproducing circuit that is less susceptible to noise and operates stably even when the running speed of the recording medium changes.

次に本考案の一実施例を図面に基いて説明する
と、1は差動増幅回路、2は情報信号入力を積分
する積分形増幅回路、3は積分形増幅回路2の出
力を規定電圧レベルで検出するレベル検出回路、
4は情報信号入力を波形のピークで検出するピー
ク検出回路、5はピーク検出回路4の出力を波形
整形する波形整形回路である。HDは磁気ヘツド
であり磁気カード等の記録媒体と情報の授受を行
なう。磁気ヘツドHDの両端は各々抵抗R1,R2
介して増幅器AMP1の入力端に接続され、増幅
器AMP1の非反転入力端は抵抗R3を介して接地
され、反転入力端と出力端は抵抗R4により接地
されている。この増幅器AMP1の出力端はコン
デンサC1の一端とコンデンサC3の一端に共通に
接続されている。コンデンサC1の他端は抵抗R4
を介して非反転入力端が接地された増幅器AMP
2の反転入力端に接続され、この反転入力端と出
力端との間にはコンデンサC2が接続されると共
にダイオードD1,D2の逆並列回路が接続されて
いる。このダイオードD1,D2は積分動作の安定
化をはかるものである。増幅器AMP2の出力端
は抵抗R5を介して反転入力端が接地された増幅
器AMP3の非反転入力端に接続され、この非反
転入力端は抵抗R6を介して増幅器AMP3の出力
端に接続されている。コンデンサC3の他端は抵
抗R7を介して非反転入力端が抵抗R6を介して接
地されている。増幅器AMP4の反転入力端に接
続され、この反転入力端との間にはダイオード
D3,D4の逆並列回路が接続されている。増幅器
AMP4の出力端は増幅器AMP5の反転入力端に
接続され増幅器AMP5の非反転入力端は抵抗R9
を介して接地されると共に抵抗R10を介してその
出力端に接続されている。増幅器AMP3の出力
端と増幅器AMP5の出力端とは抵抗値の等しい
抵抗R11と抵抗R12を介して接続され、抵抗R12
抵抗R13との接続点はダイオードD5,D6の逆並列
回路を介して増幅器AMP4の反転入力端に接続
されると共に、抵抗R13を介して接地されてい
る。このダイオードD5,D6は帰還動作の安定化
をはかるものであり抵抗R13は抵抗R11と抵抗R12
との抵抗値の差を補償するためのものである。尚
ダイオードD5,D6の逆並列回路の代りにツエナ
ーダイオードの逆直列回路を用いて同じ動作が得
られることは言うまでもない。
Next, an embodiment of the present invention will be explained based on the drawings. 1 is a differential amplifier circuit, 2 is an integral type amplifier circuit that integrates an information signal input, and 3 is an integral type amplifier circuit 2 whose output is set to a specified voltage level. Level detection circuit to detect,
4 is a peak detection circuit that detects the input information signal at the peak of the waveform; 5 is a waveform shaping circuit that shapes the output of the peak detection circuit 4; The HD is a magnetic head that exchanges information with recording media such as magnetic cards. Both ends of the magnetic head HD are connected to the input end of the amplifier AMP1 through resistors R 1 and R 2 respectively, the non-inverting input end of the amplifier AMP1 is grounded through the resistor R 3, and the inverting input end and output end are connected to the input end of the amplifier AMP1 through the resistor R 3 . Grounded by R 4 . The output end of this amplifier AMP1 is commonly connected to one end of the capacitor C1 and one end of the capacitor C3 . The other end of capacitor C 1 is resistor R 4
Amplifier AMP whose non-inverting input is grounded via
A capacitor C 2 is connected between the inverting input terminal and the output terminal, and an antiparallel circuit of diodes D 1 and D 2 is connected between the inverting input terminal and the output terminal. The diodes D 1 and D 2 are intended to stabilize the integral operation. The output terminal of the amplifier AMP2 is connected via a resistor R 5 to the non-inverting input terminal of an amplifier AMP3 whose inverting input terminal is grounded, and this non-inverting input terminal is connected via a resistor R 6 to the output terminal of the amplifier AMP3. ing. The other end of the capacitor C3 is connected via a resistor R7 , and the non-inverting input terminal is grounded via a resistor R6 . It is connected to the inverting input terminal of amplifier AMP4, and a diode is connected between this inverting input terminal.
Anti-parallel circuits of D 3 and D 4 are connected. amplifier
The output terminal of AMP4 is connected to the inverting input terminal of amplifier AMP5, and the non-inverting input terminal of amplifier AMP5 is connected to resistor R9 .
and is connected to its output terminal via a resistor R10 . The output end of the amplifier AMP3 and the output end of the amplifier AMP5 are connected through a resistor R 11 and a resistor R 12 having the same resistance value, and the connection point between the resistor R 12 and the resistor R 13 is the opposite of the diodes D 5 and D 6 . It is connected to the inverting input terminal of the amplifier AMP4 via a parallel circuit, and is grounded via a resistor R13 . These diodes D 5 and D 6 are intended to stabilize the feedback operation, and the resistor R 13 is connected to the resistor R 11 and the resistor R 12.
This is to compensate for the difference in resistance between the It goes without saying that the same operation can be obtained by using an anti-series circuit of Zener diodes in place of the anti-parallel circuit of diodes D5 and D6 .

このように構成されたこの回路の動作を説明す
る。磁気ヘツドHDによつて読み出された信号は
差動増幅回路1により増幅されて第2図のよう
な波形となる。この信号が積分形増幅回路2に入
力されると、入力信号は抵抗R4とコンデンサC2
によつて決まる時定数により積分されの様な波
形となり、カードスピードの変動による磁気ヘツ
ド再生出力レベルの変動が補償される。例えば、
カードの走行スピードが急に遅くなると、ヘツド
の再生出力の波形は第2図の○ロのようにそのレ
ベルが低下するが、波形の幅が広くなるための
波形を積分した値(面積)はスピードが変動して
も変化しない。従つて、ヘツドの再生出力波形を
積分した積分出力波形の出力レベルはスピード
変動に関係無くほぼ一定値まで上がるため、この
積分波形Bをレベル検出回路3に入力してレベル
検出すれば、カードスピードの変化による磁気ヘ
ツドの再生出力レベルの変動は補償されることに
なる。この波形をレベル検出回路3に入力して
抵抗R5,R6によつて決まる規定電圧レベルVref
でレベル検出するとの様な波形となる。又波
形はピーク検出回路4に入力される波形のピー
ク値が検出されさらに波形整形回路5により波形
整形されの様な波形となる。このとの波形
を抵抗R11,R12によつて接続するとの様な波形
となる。この波形はダイオードD5,D6を通じ
てピータ検出回路4の増幅器AMP4の反転入力
端に印加され、の斜線部で示す領域でピータ検
出回路4の作動を停止させることになる。従つて
第2図の○イの様なノイズがあつてもこの時ピー
ク検出回路4の動作は停止しているのでこのノイ
ズにより誤動作することはない。これは波形の
信号が正又は負になつている時にはダイオード
D5,D6を通して増幅器AMP4の反転入力端にバ
イアス電流が印加されているので、ピーク検出回
路4はノイズに対して作動せず、またがOVの
時には、反転入力の信号も100mv程度であるの
で、ダイオードD5,D6は導通せずこれによつて
バイアス電流は流れず、ピーク検出回路4が作動
するのである。ピーク検出回路4にはこの時帰還
電流が流れていないので高感度な動作をすること
になる。
The operation of this circuit configured in this way will be explained. The signal read out by the magnetic head HD is amplified by the differential amplifier circuit 1 and has a waveform as shown in FIG. When this signal is input to the integral amplifier circuit 2, the input signal is transmitted through the resistor R 4 and the capacitor C 2
The waveform is integrated by a time constant determined by , which compensates for fluctuations in the magnetic head reproduction output level due to fluctuations in card speed. for example,
When the running speed of the card suddenly slows down, the level of the waveform of the playback output of the head decreases as shown in Figure 2, but the value (area) of the integrated waveform that causes the width of the waveform to become wider is It does not change even if the speed changes. Therefore, the output level of the integrated output waveform obtained by integrating the reproduced output waveform of the head rises to a nearly constant value regardless of speed fluctuations, so if this integrated waveform B is input to the level detection circuit 3 and the level is detected, the card speed can be adjusted. Fluctuations in the reproduction output level of the magnetic head due to changes in the magnetic head are compensated for. This waveform is input to the level detection circuit 3 and the specified voltage level Vref is determined by the resistors R 5 and R 6 .
When the level is detected with The peak value of the waveform input to the peak detection circuit 4 is detected, and the waveform is further shaped by the waveform shaping circuit 5. When this waveform is connected through resistors R 11 and R 12 , a waveform like that is obtained. This waveform is applied to the inverting input terminal of the amplifier AMP4 of the repeater detection circuit 4 through the diodes D5 and D6 , and the operation of the repeater detection circuit 4 is stopped in the area shown by the hatched area. Therefore, even if there is a noise like the one shown in FIG. 2, since the operation of the peak detection circuit 4 is stopped at this time, this noise will not cause malfunction. This is a diode when the waveform signal is positive or negative.
Since a bias current is applied to the inverting input terminal of the amplifier AMP4 through D5 and D6 , the peak detection circuit 4 does not operate against noise, and when OV is present, the signal at the inverting input is also about 100 mV. Therefore, the diodes D 5 and D 6 are not conductive, so that no bias current flows and the peak detection circuit 4 is activated. Since no feedback current is flowing through the peak detection circuit 4 at this time, it operates with high sensitivity.

ダイオードD5,D6は前述の様に必らずしも設
けなくてもよいのであるが、これを設けない場合
には、波形の信号がOVの時にも多少の電流が
流れるので動作が不正確となるのである。尚波形
ととはOVに対して対称な波形で互いに大き
さも同じにしておくことが望ましい。
As mentioned above, the diodes D 5 and D 6 do not necessarily need to be provided, but if they are not provided, some current will flow even when the waveform signal is OV, resulting in malfunction. It will be accurate. It is desirable that the waveforms be symmetrical with respect to the OV and have the same size.

本考案は上述した構成であるので、きわめて簡
単な構成で、入力信号がスライスレベルからピー
クレベルまでの間以外は増幅器の反転入力端にバ
イアス電流が印加されることになり、この時ノイ
ズ信号であつても誤動作しない特徴がある。又積
分増幅回路を設けているので、磁気カードの走行
速度の変動や、記録密度の変動等により磁気ヘツ
ドの再生出力レベルが変動してもそれを補償でき
るので、正確なレベル検出が行なえるという優れ
た効果も有している。
Since the present invention has the above-mentioned configuration, it is an extremely simple configuration, and a bias current is applied to the inverting input terminal of the amplifier except when the input signal is from the slice level to the peak level. It has the characteristic that it will not malfunction even if it happens. Also, since it is equipped with an integral amplifier circuit, it can compensate for fluctuations in the playback output level of the magnetic head due to fluctuations in the running speed of the magnetic card, fluctuations in recording density, etc., making it possible to perform accurate level detection. It also has excellent effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の回路図、第2図は
第1図の回路の作動状態を示す波形図である。 2……積分形増幅回路、3……レベル検出回
路、4……ピーク検出回路、5……波形整形回
路、R11,R12……抵抗器。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram showing the operating state of the circuit of FIG. 1. 2... Integral amplifier circuit, 3... Level detection circuit, 4... Peak detection circuit, 5... Waveform shaping circuit, R11 , R12 ... Resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 情報信号入力を積分する積分形増幅回路と、該
積分形増幅回路の出力を規定電圧レベルで検出す
るレベル検出回路と、増幅器の反転入力端に接続
されたコンデンサと、前記増幅器の出力端及び反
転入力端の間に接続されたダイオードの逆並列回
路とを備え前記情報信号入力を波形のピークで検
出するピーク検出回路と、該ピーク検出回路の出
力を波形整形する波形整形回路とからなり、前記
レベル検出回路と波形整形回路の出力を加え合わ
せて前記ピーク検出回路を構成する上記増幅器の
反転入力端に帰還したことを特徴とする磁気再生
回路。
an integrating amplifier circuit that integrates an input information signal; a level detection circuit that detects the output of the integrating amplifier circuit at a specified voltage level; a capacitor connected to the inverting input terminal of the amplifier; The peak detection circuit includes an anti-parallel circuit of diodes connected between input terminals and detects the information signal input at the peak of the waveform, and a waveform shaping circuit that shapes the output of the peak detection circuit. A magnetic reproducing circuit characterized in that the outputs of the level detection circuit and the waveform shaping circuit are combined and fed back to the inverting input terminal of the amplifier constituting the peak detection circuit.
JP11903177U 1977-09-06 1977-09-06 Expired JPS6125057Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11903177U JPS6125057Y2 (en) 1977-09-06 1977-09-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11903177U JPS6125057Y2 (en) 1977-09-06 1977-09-06

Publications (2)

Publication Number Publication Date
JPS5446315U JPS5446315U (en) 1979-03-30
JPS6125057Y2 true JPS6125057Y2 (en) 1986-07-28

Family

ID=29073935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11903177U Expired JPS6125057Y2 (en) 1977-09-06 1977-09-06

Country Status (1)

Country Link
JP (1) JPS6125057Y2 (en)

Also Published As

Publication number Publication date
JPS5446315U (en) 1979-03-30

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