JPS628593Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a magnetic reproducing circuit used in a magnetic recording/reproducing device or the like.

Conventionally, magnetic reproducing circuits have used peak detection methods, which invert the output for each peak value of the information signal from the magnetic head to digitize the information signal, and level detection methods, which invert the output for each time the information signal reaches a certain reference value to digitize the information signal. However, the peak detection method is prone to malfunction due to noise because it outputs for each peak value of the input, and the level detection method is prone to malfunction due to noise because it outputs for each constant level value of the input.
Both types have their own drawbacks, such as the tendency for malfunctions to occur when the output level of the magnetic head fluctuates due to fluctuations in the running speed of a recording medium such as a magnetic card.

To solve this problem, a level detection method and a peak detection method are used together, and a bias current is applied to the inverting input terminal of the amplifier except when the input signal is between the level detection slice level and the peak level. There is also a device that is designed to prevent malfunction even when the device is used (Utility Application No. 119031, 1973).

However, even with this circuit system, the conventional level detection circuit is configured as shown in Figure 1, and in order to stabilize the output of the integral amplifier circuit 1, the inverse of the diodes D ₁ and D ₂ is connected. Although a parallel circuit was connected, the output of the integral type amplifying circuit 1 is unstable in direct current terms with only the anti-parallel circuit of diodes D ₁ and D ₂ , so the output of the integral type amplifying circuit 1 is Not only is it extremely difficult to set the resistors R ₁ and R ₂ of the receiving waveform shaping circuit 2, but also the level when there is no input (no signal) is unstable due to the influence of the input bias current of the amplifier. However, the NRZ recording system has not yet been able to provide a satisfactory magnetic reproducing circuit.

The present invention solves the above-mentioned conventional drawbacks by providing a magnetic reproducing circuit with stable operation, and enables stable operation to be obtained both in the level detection method and in the combined method of level detection and peak detection. be.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 2, reference numeral 11 denotes a magnetic head that reproduces information signals from a magnetic card (not shown), and resistors R ₁₁ and R ₁₂ are connected to both ends of the magnetic head 11, respectively, and the information is transmitted through the resistors R ₁₁ and R ₁₂ . The information signal reproduced by the magnetic head 11 is connected to an input terminal of an amplifier 12. The non-inverting input end of the amplifier 12 is connected to the reference potential 1/2Vcc through a resistor _R13 , while the inverting input end and output end are connected through a resistor _R14 . Therefore, the amplifier 12 and the resistors R ₁₁ , R ₁₂ ,
A differential amplification circuit 13 is configured by R ₁₃ and R ₁₄ . The output end of this amplifier 12 is commonly connected to one end of a resistor _R15 and one end of a resistor _R16 . resistance
The other end of _R15 is connected via a capacitor _C11 to the inverting input end of an amplifier 14 whose non-inverting input end is connected to the reference potential 1/2Vcc, and a resistor R is connected between this inverting input end and the output end. ₁₇ , capacitor C ₁₂ is connected,
The amplifier 14, the resistor R ₁₅ and the capacitor C ₁₁ constitute an integral amplifier circuit 15. Further, between the inverting input terminal and the output terminal of the amplifier 14, a PNP transistor Tr ₁₁ and an NPN transistor Tr ₁₂ have their respective bases connected to the inverting input terminal and their respective emitters connected to the output terminal, and two transistors. Tr ₁₁ ,
The collectors of Tr ₁₂ are connected together and the output is taken from this connection point. These two transistors Tr ₁₁ and Tr ₁₂ are connected in series so as to operate complementary to each other, and have a switching effect. The outputs taken out from the collectors of the transistors Tr ₁₁ and Tr ₁₂ are connected to the non-inverting input terminal of the amplifier 16 and the inverting input terminal of the amplifier 17, respectively. The reference potential Vcc is divided and applied by resistors R ₁₈ , R ₁₉ , R ₂₀ , and R ₂₁ . And these amplifiers 16,
Reference numeral 17 constitutes a level detection circuit that detects the output of the integral type amplifier circuit 15 at a specified voltage level.

On the other hand, the other end of the resistor R ₁₆ , one end of which is connected to the output of the amplifier 12 in the differential amplifier 13, has a non-inverting input terminal connected to the reference potential 1/2 Vcc via the capacitor C ₁₃ .
An anti-parallel circuit of diodes D ₁₁ and D ₁₂ is connected between the inverting input terminal and the output terminal of the amplifier 18 . These diodes D ₁₁ , D ₁₂ , amplifier 18 , resistor R ₁₆ , and capacitor C ₁₃ form the differential amplifier 1.
A peak detection circuit 22 is configured to detect the information signal output from 3 at the peak of the waveform. The output terminal of the amplifier 18 is connected to the inverting input terminal of the amplifier 19, and the non-inverting input terminal of the amplifier 19 is connected to the reference potential 1/2Vcc via the resistor _R22 and to the reference potential 1/2Vcc via the resistor _R23 . Connected to the output end. Amplifier 1
The output of 9 is also directly input to one input terminal of the exclusive OR circuit 20, and is connected to the other input terminal via a resistor _R24 . Since a capacitor C ₁₄ is connected between the connection point between the resistor R ₂₄ and the exclusive OR circuit 20 and the ground, the output of the amplifier 19 and the output of the amplifier 19 are connected to the exclusive OR circuit 20. the resistance
The output through an integrating circuit consisting of R ₂₄ and capacitor C ₁₄ will be added. A series circuit consisting of a resistor R _{25 and} a diode D ₁₃ and an inverter 21, and a series circuit consisting of a resistor R ₂₆ and a diode D ₁₄ are connected in parallel between one input terminal and the output terminal of this exclusive OR circuit 20. connected to resistor R ₂₅
The connection point between the resistor R26 and the diode _D13 is connected to the output of the amplifier 17, and the connection point between the resistor _R26 and the diode _D14 is connected to the output of the amplifier 16.

Next, the operation of the circuit shown in FIG. 2 constructed in this way will be explained. An information signal read out by the magnetic head 11 from a magnetic card (not shown) is amplified by a differential amplification circuit 13. The waveform of the output A of this differential amplifier circuit 13 is shown in FIG. 3a. When the output of the differential amplifier circuit 13 is input to the integral amplifier circuit 15, this input signal is passed through the resistor _R15 and the capacitor.
The output of the integral type amplifier 15 has the waveform shown in FIG _. 3b, and any fluctuations in the playback output level of the magnetic head due to fluctuations in card speed are compensated for here. be done. The output of the integral amplifier 15 is shaped into the waveform shown in FIG. 3b by switching one of the two transistors Tr ₁₁ and Tr ₁₂ which operate complementary to each other. That is, the first small pulse (noise) shown in FIG. 3a does not reach the switching level of transistor Tr ₁₂ , so transistor Tr ₁₂ does not turn on.
Since both transistors Tr ₁₁ and Tr ₁₂ remain off, the output C is held at 1/2Vcc. Next _, when the second and subsequent positive pulses _shown in FIG. It is lowered to the level of the negative side pulse shown in b. Conversely, when the negative pulse shown in FIG. 3a is input, the transistor Tr ₁₁ is turned on, and the collector of the transistor Tr ₁₁ , that is, the output C, is raised to the level of the positive pulse shown in FIG. 3 b. Therefore, the first small pulse (noise) shown in FIG. 3a does not operate the transistors Tr ₁₁ and Tr ₁₂ and is not taken out as an output, and the rising and falling edges of each pulse are also made clear, as shown in FIG. 3C. The output waveform shown in is sent to amplifiers 16 and 17.

On the other hand, the output from the differential amplifier circuit 13 shown in FIG. 3a is also input to the peak detection circuit 22. Since the polarity of the peak detection circuit 22 changes when the head output changes, the output F of the amplifier 18 has a waveform as shown in FIG. 3f. The output F of this amplifier 18 is input to the amplifier 19, and the output G is inverted and waveform-shaped to have the waveform shown in FIG. 3g. The output G of the amplifier 19 is an exclusive
OR circuit 20 directly and resistor R ₂₄ and capacitor C ₁₄
The output _of the circuit 20 produces an output only when there _is an input signal in only _one of the two inputs.
At the connection point I with D ₁₄ , outputs having the waveforms shown in FIG. 3 h and i are tentatively generated.

On the other hand, the collector outputs of the switching transistors Tr ₁₁ and Tr ₁₂ are connected to the amplifier 16, and the amplifier 16 divides the reference potential Vcc between the resistor R ₁₈ and the resistors R ₁₉ , R ₂₀ , R ₂₁ , and Since it works as a comparator based on potential, Figure 3C
The final output D of the amplifier ₁₆ is output only when a positive pulse is input in the _waveform of The waveform shown in FIG. d is output as the final output D. This final output D
is the output corresponding to the negative pulse signal shown in FIG. 3a among the information signals reproduced by the magnetic head 11.

Further, the collector outputs of the switching transistors Tr ₁₁ and Tr ₁₂ are connected to the amplifier 17, and the amplifier 17 connects the reference potential Vcc to the resistors R ₁₈ and Tr 12 .
Since it works as a comparator based on the potential divided by R ₁₉ , R ₂₀ and resistor R ₂₁ , it emits an inverted output only when a negative pulse in the waveform shown in FIG. As for E, when the output coincides with the output generated at the connection point H between the resistor R ₂₅ and the diode D ₁₃ , that is, the waveform shown in FIG. 3e is output as the final output E. This final output E is an output corresponding to the positive pulse signal shown in FIG. 3a among the information signals reproduced by the magnetic head 11 (however, noise has been removed).

Of the signals reproduced from the magnetic head 11 in the manner described above, information signals of unknown polarity can be reliably read out without picking up noise.

As described above, the present invention integrates the information signal input reproduced by the magnetic head using the integral amplifier, and then detects the output of the integral amplifier at a specified voltage level using the level detection circuit. In a magnetic reproducing circuit configured to obtain an information signal, two switching transistors connected in series and operating complementary to each other are connected between the input and output of the integral amplifier, and the voltage between the input and output is The above-mentioned switching transistor is switched at the same time as the output is taken out from the connection point of the above-mentioned switching transistor and connected to the above-mentioned level detection circuit, so that a DC stable information signal is input to the level detection circuit. It is possible to prevent malfunctions. Furthermore, since a stable information signal is input to the level detection circuit, the setting of the level detection circuit itself can be made very simple.

Therefore, if the present invention is used even in devices such as manual card readers where the running speed of the recording medium varies greatly, stable information signal reproduction can be performed.
There is no need to provide a read discard bit, which is conventionally used.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram illustrating a conventional level detection circuit, FIG. 2 is a circuit diagram illustrating an embodiment of the present invention, and FIG. 3 is a waveform diagram illustrating the operation of FIG. 2. 11...Magnetic head, 13...Differential amplifier circuit,
15... Integral type amplifier circuit, Tr ₁₁ , Tr ₁₂ ... Transistor, 16, 17... Amplifier, 22... Peak detection circuit.

Claims (1)

[Scope of utility model registration request] A magnetic reproducing circuit configured to integrate an information signal input reproduced by a magnetic head using an integrating amplifier, and then detecting the output of the integrating amplifier at a specified voltage level using a level detection circuit to obtain a desired information signal. wherein the bases of two switching transistors of different conductivity types are connected to the inverting input terminal of the integrating amplifier, and the emitters of the two transistors are respectively connected to the output terminal of the integrating amplifier; Magnetic regeneration characterized in that the switching transistor is switched by the potential difference between the inverting input terminal and the output terminal, and the output is taken out from a connection point between the collectors of the two switching transistors and connected to the level detection circuit. circuit.