JPH07169003A - Signal reproducing circuit for magneto-resistance effect type head - Google Patents

Abstract

PURPOSE:To avoid the superposition of an unnecessary component on a reproducing signal and thereby minimize the loss of the data capacity of the signal reproducing circuit of a magnetic recording/reproducing apparatus in which an MR head is used by reducing an idle period which is a transition state from a writing state to a reading state. CONSTITUTION:Transistors 7 and 8 which amplify a reproducing signal appearing between both the terminals of MR head 1 at the time of reading, a capacitor 9 which is connected to between the respective emitters of the transistors 7 and 8 and circuits 12 to 17 which control a voltage VC between the terminals of the capacitor 9 in accordance with a read/write control signal R/W are provided. A voltage information corresponding to a voltage which appears between the terminals of the capacitor 9 is stored when the state is decided to be a reading state and a voltage corresponding to the stored voltage information is applied between the terminals of the capacitor when the state is decided to be a writing state and when the state is judged to be a transition period from the writing state to the reading state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal reproducing circuit in a magnetic recording / reproducing apparatus, and more particularly to a magnetoresistive effect (Magnet resistance effect).
When reproducing data on a magnetic recording medium by a reproducing head (hereinafter referred to as an MR head) using an element utilizing an o-Resistive effect, a write state is caused by a voltage between terminals of the MR head. The present invention relates to a technique for promptly recovering a transient phenomenon that occurs when transitioning to a read state.

In recent years, a magnetic recording / reproducing apparatus such as a magnetic disk apparatus has been increased in speed and capacity, and accordingly, in order to enable a higher recording density of a magnetic head, an ordinary inductive thin film magnetic head is MR heads have come to be used only for reproducing data. This is because when an MR head is used for reproducing data, it is possible to detect a signal magnetic field that does not depend on the relative speed between the MR head and the magnetic recording medium, so that the running speed of the magnetic recording medium is reduced and the recording density is increased. Because you can. On the other hand, however, the MR head causes an undesired transient phenomenon when the write state changes to the read state due to the voltage difference across the MR head. Therefore, there is a demand for a technique for eliminating such a transient phenomenon.

[0003]

2. Description of the Related Art FIG. 5 shows the configuration of a conventional MR head signal reproducing circuit. In the figure, MR
One terminal of the head 1 is connected to a high-potential power supply line V ₁ (for example, 5 V) via a resistor 2 and is also used as a base of an NPN transistor 7 which constitutes a first stage reproducing amplifier (read amplifier). The other terminal of the MR head 1 is connected to the low-potential power supply line V ₂ (for example, 0 V) via the resistor 3 and the constant current source 4 and also constitutes the NPN which constitutes the first stage read amplifier. It is connected to the base of the transistor 8. The collector of transistor 7 is
It is connected to the output terminal RX and is also connected to the power supply line V ₁ via the resistor 5, and the collector of the transistor 8 is connected to the output terminal RY and is also connected to the power supply line V ₁ via the resistor 6. It is connected to the. The emitter of the transistor 7 is connected to one terminal CX of the capacitor 9.
Is connected to the power supply line V ₂ via the constant current source 10, and the emitter of the transistor 8 is
It is connected to the other terminal CY of the capacitor 9 and also connected to the power supply line V ₂ via the constant current source 11.
Further, the output terminals RX and RY are connected to a demodulation system (including an amplifier, a demodulation circuit, etc.) at the next stage (not shown).

The constant current sources 4, 10 and 11 are turned on / off in response to a write gate signal WG generated based on a read / write control signal (described later). In the illustrated example, when the write gate signal WG is at "L" level (that is, at the time of reading), the constant current sources 4, 10 and 11 are turned on to supply the constant currents Is, Ib and Ib, respectively, and write When the gate signal WG is at the "H" level (that is, at the time of writing), the constant current sources 4, 10 and 11 are turned off to interrupt the constant current supply.

Therefore, at the time of reading, the power supply line V ₁
The current supplied from the power source flows through the resistor 2, the MR head 1, the resistor 3 and the constant current source 4 to the power supply line V ₂ , and the power source via the resistor 5, the transistor 7 and the constant current source 10. with flowing in the line V _2, resistors 6, flows to the power supply line V ₂ through the transistor 8 and the constant current source 11.

When a current Is (which is a sense current for detecting a magnetic field applied to the magnetic recording medium) flows through the MR head 1, a potential difference is generated across the MR head 1 due to its internal resistance, and the transistor is accordingly responded. An offset voltage is generated between the base of transistor 7 and the base of transistor 8. Therefore, the current flowing through the transistor 7 becomes larger than the current flowing through the transistor 8, and the output terminal RX
A potential difference corresponding to the offset voltage is also generated between the output terminal RY and the output terminal RY.

The capacitor 9 appropriately charges or discharges electric charges so as to eliminate this potential difference, that is, the offset voltage. Since the voltage VC between the terminals of the capacitor 9 balances the emitter voltages of the transistors 7 and 8, currents of Ib flow through the transistors 7 and 8, respectively. Therefore,
Between the output terminals RX and RY (output signal VR), a change in voltage due to a change in internal resistance of the MR head 1 due to a change in magnetic field, that is, a signal whose amplitude changes in response to a change in magnetic field (that is, A reproduced signal) is output, and ideally, an unnecessary offset voltage is not transmitted.

[0008]

FIG. 6 shows an example of operation timing waveforms of the circuit of FIG. In the figure,
RG and WG represent a read gate signal and a write gate signal, respectively. The read gate signal RG is a signal for setting a period during which data can be normally read from the magnetic recording medium, falls when the read / write control signal R / W changes to “L” level, and then reads / writes. It rises after a predetermined idle period has elapsed when the control signal R / W changes to "H" level. On the other hand, the write gate signal W
G is a signal for setting a period during which data can be normally written to the magnetic recording medium, and is a read / write control signal R
It rises after a predetermined idle period when / W changes to "L" level, and falls when the read / write control signal R / W changes to "H" level. That is, the idle period is defined by the period from the time when the read / write control signal R / W changes in level to the rise of the read gate signal RG or the write gate signal WG.

As described above, in the MR head 1, it is necessary to apply the bias magnetic field to flow the sense current Is in the read state, which causes an offset voltage across the MR head 1. Therefore, in the first stage read amplifier (transistors 7 and 8), in order to prevent the amplification of the offset voltage, the current Ib is caused to flow by the constant current sources 10 and 11, so that the potential difference corresponding to the offset voltage is applied between the terminals CX and CY of the capacitor 9. V ₀ is given. For example, when the resistance value of the MR head 1 is 15Ω and the sense current Is is 20 mA, the potential difference VC across the MR head 1 is 300 m.
It becomes V. In this way, the offset voltage appearing at both ends of the MR head 1 is canceled by the capacitor 9.
As a result, the output signal VR appearing between the output terminals RX and RY
Is 0 (that is, the offset voltage is 0), and no problem occurs.

On the other hand, in the write state, it is necessary to cut off the sense current Is in order to prevent deterioration of the MR element and reduce power consumption. At this time, since no offset voltage is generated across the MR head 1, the inter-terminal voltage V of the capacitor 9 is
C also becomes 0. Therefore, the output signal VR appearing between the output terminals RX and RY also becomes 0 (that is, the offset voltage is 0), and no problem occurs.

However, a problem arises during the transition from the write state to the read state (during a transient period called an idle period in FIG. 6). That is, during this transition period, the charge corresponding to the potential difference V ₀ (300 mV in the above example) corresponding to the offset voltage is accumulated in the capacitor 9, but during the idle period, the charge is roughly according to the time constant. It takes a few μs. During this period, the offset voltage of the MR head 1 is not completely canceled by the capacitor 9, so that the output signal VR has a transient effect according to the offset voltage. Since this hinders signal reproduction, it is preferable that the transitional idle period is as short as possible.

As described above, in the conventional MR head signal reproducing circuit, an unnecessary offset voltage is superposed on the reproduced signal during the idle period in which the write state transits to the read state, so that accurate demodulation cannot be performed. There was a point. In addition, since the data cannot be read from the magnetic recording medium during the idle period (that is, during the transient phenomenon) in which the offset voltage appears, the storage capacity of the magnetic disk device must be reduced accordingly, resulting in However, there is an inconvenience that the data capacity is lost.

The present invention was created in view of the above problems in the prior art. In a magnetic recording / reproducing apparatus using an MR head, an unnecessary offset component is shortened by shortening an idle period during which a write state changes to a read state. It is an object of the present invention to provide a signal reproducing circuit capable of preventing data from being superposed on a reproduced signal and minimizing loss of data capacity.

[0014]

In order to solve the above problems, according to the present invention, a potential difference equal to the potential difference appearing at both ends of the capacitor in the read state is applied to the capacitor in the write state and in the transition from the write state to the read state. It is applied between the terminals. That is, the magnetoresistive head signal reproducing circuit according to the present invention is configured such that the first and second power supply lines having different voltages are connected to the first power supply line through a resistor at one end, A magnetoresistive head that sometimes reproduces a signal from a magnetic recording medium and a second end of the magnetoresistive head are connected through a resistor and between the resistor and the second power supply line. And a first constant current source for supplying a sense current to the magnetoresistive head in a read state and a collector connected to the first power supply line via a resistor, respectively. First and second transistors respectively responsive to voltage signals obtained from one end and the other end of the resistance effect head, and between the respective emitters of the first and second transistors and the second power supply line, This Connected, first and second and third constant current sources respectively supply predetermined constant current to the second transistor, the emitter and the second of said first transistor when the read state
And a capacitor connected between the emitters of the transistors, and voltage information corresponding to the voltage appearing between the terminals of the capacitor when the read state is determined based on the read / write control signal. A control circuit that applies a voltage corresponding to the stored voltage information between the terminals of the capacitor when the write state is determined based on the signal and when the transition period from the write state to the read state is determined. It is characterized by doing.

[0015]

According to the above-described configuration of the present invention, the control circuit stores the voltage appearing between the terminals of the capacitor in the read state, and the stored voltage is stored in the write state and from the write state to the read state. The voltage is controlled to be applied across the terminals of the capacitor during the transition to. As a result, the same voltage value as that in the read state is obtained without changing the voltage between the terminals of the capacitor during the read state, the write state, and the entire transition period between the write state and the read state. Can be maintained at.

Therefore, the charging time of the capacitor becomes unnecessary, and as a result, the idle period in which the write state changes to the read state is shortened, so that an unnecessary offset voltage as seen in the conventional type is superimposed on the reproduction signal. Inconvenience (transient phenomenon) can be eliminated. Further, since the period during which data can be read from the magnetic recording medium becomes longer as the idle period becomes shorter, the loss of data capacity can be minimized.

The details of other structural features and operations of the present invention will be described with reference to the embodiments described below with reference to the accompanying drawings.

[0018]

FIG. 1 shows the circuit configuration of a first embodiment of a signal reproducing circuit for an MR head according to the present invention. In the figure, the same reference numerals as those used in the conventional configuration of FIG. 5 represent the same constituent elements, and the description thereof will be omitted.

In addition to the configuration shown in FIG. 5, the signal reproducing circuit according to the present embodiment has an analog / digital (A / D) converter 12 for converting the voltage VC appearing between the terminals CX and CY of the capacitor 9 into a digital signal. And A / corresponding to the voltage appearing between the terminals CX and CY of the capacitor 9 in the read state.
A memory (for example, RAM) 13 for storing the digital output value of the D converter 12, and a read / write control signal R
Microprocessor unit (MPU) 1 for controlling the writing of the digital output value of the A / D converter 12 to the memory 13 and the reading control from the memory in response to / W.
4, a digital / analog (D / A) converter 15 for converting the digital output value of the A / D converter 12 read from the memory 13 into an analog signal, and the collectors of the power line V ₁ And the capacitor 9
Each of the terminals CX and CY of the N is connected to the respective emitters thereof, and N is responsive to the output signal of the D / A converter 15 respectively.
It is characterized in that PN transistors 16 and 17 are provided.

The transistors 16 and 17 have a function of converting the output signal of the D / A converter 15 into a signal of lower impedance and supplying it to the capacitor 9 (that is, a function as an emitter follower). In this case, the voltage applied between the terminals CX and CY of the capacitor 9 is D / A.
From the output voltage level of the converter 15, transistors 16 and 1
It exhibits a level lower by 7 base-emitter voltages.
Therefore, in the MPU 14, it is necessary to appropriately perform calculation so that the output voltage of the D / A converter 15 becomes higher by the base-emitter voltage of the transistors 16 and 17.

The MPU 14 is for controlling the entire magnetic disk device (described later) to which the present embodiment is applied, and uses a part of its functions for the control described below. That is, when the MPU 14 determines the read state based on the read / write control signal R / W, A
The digital output value corresponding to the voltage VC appearing between the terminals CX and CY of the capacitor 9 obtained through the / D converter 12 is controlled to be stored in the memory 13, and the write state is controlled based on the read / write control signal R / W. It is controlled to supply the digital output value of the A / D converter 12 stored in the memory 13 to the D / A converter 15 when the determination is made and when the transition period from the write state to the read state is determined. As a result, the output signal of the D / A converter 15 is
After being converted into a low impedance signal through the transistors 16 and 17, it is applied between the terminals CX and CY of the capacitor 9.

The digital output value corresponding to the voltage VC appearing between the terminals CX and CY of the capacitor 9 is stored in the memory 1.
The control for storing in 3 is performed when the product is shipped or when the user uses it (for example, when the power is turned on and the first read command is input). FIG. 2 shows an example of operation timing waveforms of the circuit of FIG. In the circuit configuration of this embodiment, the MPU 14, the A / D converter 12, the memory 13, the D /
A converter 15 and emitter follower transistor 16,
Due to the cooperative action of 17, the capacitor 9 in the lead state is
Voltage V ₀ appearing across the terminals (300 mV in the illustrated example)
Is converted into a digital value through the A / D converter 12, voltage information of the digital value is stored in the memory 13, and the stored voltage information is in the write state and during the transition from the write state to the read state. It is controlled so that it is read from the memory 13, converted into an analog voltage through the D / A converter 15, and further applied between the terminals of the capacitor 9 through the transistors 16 and 17. Therefore,
As shown in the operation timing chart of FIG. 2, the inter-terminal voltage VC of the capacitor 9 is changed during the read state and the write state, and during the entire transition period between the write state and the read state. It is possible to maintain the same voltage value of 300 mV as in the read state.

As a result, the charging time of the capacitor 9 becomes unnecessary, and as a result, the transition period (idle period) from the write state to the read state is shortened, so that a transient phenomenon (unnecessary offset voltage) occurs at the transition. Can be prevented. Further, since the period during which data can be read from the magnetic recording medium becomes longer as the idle period becomes shorter, the loss of data capacity can be minimized.

The MR used in this embodiment is shown in FIG.
The configuration of the head is shown. In the figure, (a) is MR
1 is a perspective view showing the structure of the entire recording / reproducing head including the head, and FIG. 1B is an enlarged view of a portion P of FIG. In FIG. 3A, reference numeral 21 indicates a slider of a recording / reproducing head, and a recording / reproducing magnetic head (portion indicated by P) is formed on the end surface thereof by using a vacuum thin film forming technique or the like. As shown in FIG. 3B, this thin film magnetic head is an MR as a reproducing head formed in a thin film on a shield member 31.
The element 1 is further provided with a recording current supply coil 35 and an inductive head 37 as a recording head, which are laminated on the element 1 via a shielding thin film 33. Reference numeral 39 is a lead for supplying a sense current to the MR element 1, and 41 is a track on which data is recorded. Further, in FIG. 3A, 23A and 23B respectively represent pads connected to the terminals of the coil 35,
Similarly, 25A and 25B respectively represent pads connected to the leads 39 (there are actually two) of the MR element 1.

FIG. 4 shows the structure of a magnetic disk device to which this embodiment is applied. In the figure, (a)
Shows a structure seen in a plane, and (b) shows a structure seen in a cross section. Referring to FIG. 4, the magnetic disks 50 are arranged inside the disk enclosure 100, and in the illustrated example, six magnetic disks 50 (see FIG. 4B) are rotatably provided by a disk rotation unit 52. . The slider 21 of the recording / reproducing head is attached to the tip of the arm 56 of the head actuator 54, and the voice coil motor (V
CM) 60. In addition, the magnetic disk 50
A plurality of data recording areas (for example, 100
0 to 1500) tracks 62 are formed concentrically. A portion of these tracks (eg, the outer peripheral portion) is used to record servo data, which is illustrated as a measuring cylinder 64.

[0026]

As described above, according to the present invention, the first stage read amplifier is provided in the read state, the write state, and the entire transition period between the write state and the read state. By controlling the voltage across the terminals of the selected capacitor to be constant, it is possible to eliminate the need to charge the capacitor during the transition from the write state to the read state, thereby reducing the idle time. It is possible to prevent the occurrence of unnecessary transient phenomena, and thus to minimize the loss of data capacity.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of a signal reproducing circuit for an MR head according to the present invention.

FIG. 2 is an operation timing chart of the circuit of FIG.

3A and 3B are views for explaining the MR head used in the embodiment of FIG. 1, in which FIG. 3A is a perspective view showing the structure of the entire recording / reproducing head, and FIG. 3B is a part of P in FIG. FIG.

4A and 4B are views showing the structure of a magnetic disk device to which the embodiment of FIG. 1 is applied, in which FIG. 4A is a plan view and FIG.

FIG. 5 is a circuit configuration diagram of a conventional MR head signal reproducing circuit.

6 is an operation timing chart of the circuit of FIG.

[Explanation of symbols]

1 ... MR (magnetoresistive effect type) head 2, 3, 5, 6 ... Resistor 4, 10, 11, ... Constant current source 7, 8, 16, 17 ... NPN transistor 9 ... Capacitor 12 ... A / D converter 13 Memory (RAM) 14 Means for controlling writing / reading to the memory (MPU) 15 D / A converter Is ... Sense current flowing in MR head Ib ... Constant current flowing in read amplifier transistor R / W ... Read / write (R / W) control signal RG ... read gate signal VC ... voltage WG ... write gate signal V ₁ appearing between the capacitor terminals, V ₂ ... power supply line (power supply voltage)

Claims (3)

[Claims] 1. A first and a second power supply line (V ₁ , V ₂ ) having different voltages, and one end connected to the first power supply line via a resistor (2). The magnetoresistive head (1) for reproducing a signal from a recording medium and the other end of the magnetoresistive head are connected via a resistor (3) and the resistor and the second A first constant current source (4), which is connected between power supply lines and supplies a sense current (Is) to the magnetoresistive head during a read state, and a resistor (5) on each of the first power supply lines. First and second transistors (7, 8) which are connected to respective collectors via the first and second ends of the magnetoresistive head and respectively respond to voltage signals obtained from one end and the other end of the magnetoresistive head, Each of the emitters of the first and second transistors and the second
Are connected between the power supply lines of the first and second power supply lines, and a predetermined constant current (I
b) second and third constant current sources (1
0, 11) and a capacitor (9) connected between the emitter of the first transistor and the emitter of the second transistor.
When the read state is determined based on the read / write control signal (R / W), voltage information corresponding to the voltage (VC) that appears between the terminals of the capacitor is stored, and the read / write control signal is stored.
When determining the write state based on the write control signal and when determining the transition period from the write state to the read state,
A control circuit (12 to 17) for applying a voltage corresponding to the stored voltage information between the terminals of the capacitor, and a signal reproducing circuit for a magnetoresistive head. 2. The A / D converter (12) for converting the voltage appearing between the terminals of the capacitor into a digital signal, and the control circuit corresponding to the voltage appearing between the terminals of the capacitor in a read state. A memory (13) for storing an output value of the A / D converter, and a writing control of the output value of the A / D converter to the memory in response to the read / write control signal, and a memory from the memory. A read control means (14) and a D / which converts the output value of the A / D converter read from the memory into an analog signal.
An A converter (15).
A signal reproducing circuit for a magnetoresistive effect head according to 1. 3. The control circuit includes third and fourth transistors (16, 17) each having a collector connected to the first power supply line and responsive to an output signal of the D / A converter. 3. Further comprising, the signal obtained from the emitters of the third and fourth transistors is applied between the terminals of the capacitor.
A signal reproducing circuit for a magnetoresistive effect head according to 1.