JPH117602A - Signal regenerative circuit for magneto-resistance effect type head - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a superposing of needless offset component on a regenerative signal and to minimize the loss of data capacity by shortening to the minimum a trangent period to change over from an idle state to a lead state or a trangent period to changeover the head in a lead state regarding the signal regeneration circuit in a magnetic recording regenerative unit making use of MR head. SOLUTION: This circuit is equipped with a constant current source 4 to supply sense current Is to MR head 1 at the time of load state, a constant current sources 10, 11 to supply constant current Ia to a pair ol regenerative transistor 7, 8 at the time of lead state, and capacitors connected between the emitters of each of the transistors. Further, this circuit is constituted so that the constant current sources 13, 14 supplying a constant current Ib are respectively connected with constant current sources 10, 11 in parallel, and the constant current sources 13, 14 are made to be ON only for a prescribed duration of time when a command is given to change over from an idle state to a lead state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal reproducing circuit in a magnetic recording / reproducing apparatus, and more particularly, to a magnetoresistive effect (Ma).
When data on a magnetic recording medium is reproduced by a reproducing head (hereinafter, referred to as an “MR head”) using an element utilizing a gneto-resistive effect, the voltage is caused by a voltage between terminals of the MR head. The present invention relates to a technique for quickly recovering a transient phenomenon that occurs when switching from the idle state to the read state or when switching the head in the read state.

In recent years, the speed and capacity of magnetic recording / reproducing devices such as magnetic disk devices have been increased, and accordingly, magnetic heads have been replaced with ordinary inductive thin film magnetic heads in order to enable higher recording density. MR heads have been used exclusively for data reproduction. This is because, when an MR head is used for data reproduction, a signal magnetic field can be detected independent of the relative speed between the MR head and the magnetic recording medium, so that the running speed of the magnetic recording medium is reduced to increase the recording density. Because you can do it. However, on the other hand, an undesired transient phenomenon occurs when the MR head is switched from the idle state to the read state or when the head is switched in the read state due to the voltage between the terminals, as described later. Therefore, there is a demand for a technique for eliminating such a transient phenomenon.

[0003]

2. Description of the Related Art FIG. 7 shows a configuration of a conventional signal reproducing circuit for an MR head, and FIG. 8 shows an operation timing waveform thereof. In FIG. 7, one terminal of an MR head 1 is connected to a connection line 90 and a high-potential power supply line V ₁ (for example, 5 V) via a resistor 2, and a first-stage reproducing amplifier (read amplifier). And the other terminal of the MR head 1 is connected to a low-potential power supply line V ₂ (for example, 0 V) via a resistor 3 and a constant current source 4. , Is connected to the base of an NPN transistor 8 constituting a first-stage read amplifier. The collector of transistor 7
The output terminal RX is connected to the power supply line V ₁ via the resistor 5. The collector of the transistor 8 is connected to the output terminal RY and is connected to the power supply line V ₁ via the resistor 6. It is connected to the. The emitter of the transistor 7 is connected to one terminal CX of the capacitor 9.
And connected to the power supply line V ₂ via the constant current source 10, and the emitter of the transistor 8 is connected to
It is connected to the other terminal CY of the capacitor 9 and to the power supply line V ₂ via the constant current source 11.
The output terminals RX and RY are connected to a demodulation system (not shown).

In addition, CE is a chip enable signal, R /
W indicates a read / write control signal, and 12 indicates an AND gate which responds to the chip enable signal CE and the read / write control signal R / W. The constant current source 4 turns on / off in response to the chip enable signal CE, while the constant current sources 10 and 11 turn on / off in response to the output of the AND gate 12, respectively. The magnetic recording / reproducing apparatus including this circuit is set to an idle state when the chip enable signal CE is at "L" level, and is set to a read / write state when it is at "H" level. The read state is selected when the read / write control signal R / W is at "H" level, and the write state is selected when it is at "L" level.

In this configuration, when the chip enable signal CE is at "L" level (that is, in an idle state), the constant current sources 4, 10, and 11 are all off. When the chip enable signal CE is at "H" level, the constant current source 4 is turned on to supply the constant current Is, and when the chip enable signal CE is at "H" level and the read /
When the write control signal R / W is at the “H” level (that is, in the read state), the constant current sources 10 and 11 are turned on to supply the constant current Ia.

Therefore, in the read state, the power supply line V₁
From the connection line 90, the resistor 2, M
Power line is connected via R head 1, resistor 3 and constant current source 4.
V _TwoA resistor 5, a transistor 7, and a constant current source 10
Power line V through_Two, Resistor 6, transistor 8
And the power supply line V via the constant current source 11_TwoTo each
Flow in.

When a constant current Is (this is a sense current for detecting a magnetic field applied to a magnetic recording medium) flows through the MR head 1, the internal resistance of the MR head 1 causes the resistance Is to flow.
, An offset voltage is generated between the base of the transistor 7 and the base of the transistor 8. Therefore, the current flowing through the transistor 7 becomes larger than the current flowing through the transistor 8, and the output terminal R
A potential difference corresponding to the offset voltage also occurs between X and RY.

The capacitor 9 appropriately charges or discharges electric charge so as to eliminate the potential difference, that is, the offset voltage. In order to balance the emitter voltages of the transistors 7 and 8 with the terminal voltage VC of the capacitor 9, a constant current Ia from the constant current sources 10 and 11 flows through the transistors 7 and 8, respectively. Therefore, between the output terminals RX and RY (output signal VR), there is a voltage change due to a change in the internal resistance of the MR head 1 due to a change in the magnetic field, that is, a signal whose amplitude changes in response to the change in the magnetic field. (That is, a reproduced signal) is output, and ideally, an unnecessary offset voltage is not transmitted.

[0009]

As described above, in the MR head 1, it is necessary to apply a bias magnetic field to flow the sense current Is in the read state, so that an offset voltage is generated at both ends of the MR head 1. . Therefore, in the first-stage read amplifier (transistors 7 and 8), the currents Ia are supplied by the constant current sources 10 and 11 to prevent the amplification of the offset voltage, so that the terminals CX and C
A potential difference V ₀ corresponding to the offset voltage is given between Y (see FIG. 8). That is, the offset voltage appearing at both ends of the MR head 1 is canceled by the action of the capacitor 9. As a result, the output signal VR appearing between the output terminals RX and RY becomes 0 (that is, the offset voltage is 0), and no problem occurs.

On the other hand, in the idle state, it is necessary to cut off the sense current Is in order to prevent the deterioration of the MR element.
At this time, since no offset voltage is generated at both ends of the MR head 1, the terminal voltage VC of the capacitor 9 also becomes zero.
Therefore, the output signal V appearing between the output terminals RX and RY
R is also 0 (that is, the offset voltage is 0), and no problem occurs.

However, a problem arises during such a transitional period of switching from the idle state to the read state.
That is, during this transition period, the state where the voltage between terminals of the capacitor 9 is VC = 0 (the state in which no charge is stored in the capacitor 9) is changed to the state where VC = V ₀ (the state of the capacitor 9).
(In the state where the electric charge corresponding to the potential difference corresponding to the offset voltage is accumulated), it is necessary to make the transition immediately, ideally, instantaneously. However, since the capacitor 9 has a corresponding time constant, this ideal It is practically impossible to realize a proper state transition. Therefore, during this transition period, the offset voltage of the MR head 1 cannot be completely canceled by the capacitor 9, and the output signal VR has a transient effect corresponding to the offset voltage (in FIG. "Voltage) appears. This hinders the reproduction of the signal, so it is preferable that the transition period be as short as possible.

In the case of a signal reproducing circuit having a plurality of MR heads, the same problem as described above occurs when the head is switched in the read state. That is, the internal resistances of the MR heads are not always the same, but rather, the internal resistances usually vary due to processes and the like. In such a situation, when the head is switched in the read state, the voltage between the terminals of the MR head fluctuates due to the difference in the internal resistance during the transitional period of the switching, and the voltage between the terminals of the capacitor 9 is accordingly changed. The voltage VC also fluctuates. As a result, the output signal V
R has a transient effect (a voltage similar to the “whisker-like” voltage shown in FIG. 8) corresponding to the fluctuation of the inter-terminal voltage VC.

As described above, in the conventional signal reproducing circuit for the MR head, an unnecessary offset voltage is superimposed on the reproduced signal during the transitional period of switching from the idle state to the read state or during the transition period of switching the head in the read state.
Therefore, there is a problem that accurate demodulation cannot be performed. Also, data cannot be read from the magnetic recording medium during the transition period when the offset voltage appears,
A gap portion (dataless portion) having a length corresponding to the transition period is formed between the data blocks, and the storage capacity of the magnetic disk drive must be reduced accordingly, resulting in a data loss. There was a disadvantage that the capacity was lost.

The present invention has been made in view of the problems in the prior art, and in a magnetic recording / reproducing apparatus using an MR head, a transition period for switching from an idle state to a read state or a transition period for switching a head in a read state is described. It is an object of the present invention to provide a signal reproducing circuit capable of suppressing unnecessary offset components from being superimposed on a reproduced signal by shortening the signal as much as possible, thereby minimizing a loss of data capacity.

[0015]

According to a first aspect of the present invention, there is provided a first and second power supply lines having different voltages, the first power supply line, and a lead state. At one end, one end of an MR head for reproducing a signal from a magnetic recording medium, a connection line connected via a resistor,
A first constant current connected to the other end of the MR head via a resistor and connected between the resistor and the second power supply line to supply a sense current to the MR head in a read state; A source and a pair of transistors connected to the first power supply line via respective resistors, respectively, and each of which responds to a voltage signal obtained from one end and the other end of the MR head; Second and third constant current sources respectively connected between the emitters of the transistors and the second power supply line and supplying a constant current to the pair of transistors in a read state, respectively. A capacitor connected between the emitters of the transistor; fourth and fifth constant current sources connected in parallel to the second and third constant current sources, respectively; It toggles the MR head signal reproducing circuit, characterized in that it comprises a circuit for controlling to turn on the constant current source only the fourth and fifth predetermined time when instruction is provided.

According to the configuration based on the first embodiment, when the switching from the idle state to the read state is commanded, the control is performed so that the fourth and fifth constant current sources are turned on for a predetermined time. Therefore, during this predetermined time, the pair of transistors constituting the read amplifier include the second and third transistors.
In addition to the original constant current by the constant current source of
Additional constant current flows from the constant current source. That is, each emitter current of the read amplifier transistor temporarily increases. As a result, the charge supplied to the capacitor temporarily increases, and the capacitor can be quickly charged to a predetermined potential.

As described above, the charging time of the capacitor is relatively shortened, and as a result, the transition period for switching from the idle state to the read state is shortened. Can be suppressed. Further, the period during which data can be read from the magnetic recording medium is lengthened by the shortened transition period, and loss of data capacity can be minimized.

According to the second aspect of the present invention, the first and second power supply lines having different voltages, the first power supply line, and the MR for reproducing a signal from the magnetic recording medium in the read state One end of the head is connected via a resistor to one end of the head, and the other end of the MR head is connected via a resistor and connected between the resistor and the second power supply line; A first constant current source for supplying a sense current to the MR head in a read state, and respective collectors connected to the first power supply line via respective resistors;
A pair of transistors respectively responding to voltage signals obtained from one end and the other end of the MR head, respectively connected between each emitter of the pair of transistors and the second power supply line, and in a read state; Second and third constant current sources for respectively supplying a constant current to the pair of transistors, a capacitor connected between the emitters of the pair of transistors, and a lead state in an idle state. And a dummy head circuit for providing a potential difference corresponding to an offset voltage appearing at both ends of the MR head at times.

According to the configuration based on the second embodiment, the potential difference corresponding to the offset voltage appearing at both ends of the MR head in the read state is applied to the capacitor in the idle state by the dummy head circuit. In addition, when switching from the idle state to the read state, the fluctuation of the voltage between the terminals of the capacitor can be minimized.
In other words, when switching from the idle state to the read state,
In order to charge a capacitor to a predetermined potential (VC = V ₀ in FIG. 8), it is necessary to start charging from a state where the voltage between terminals of the capacitor is 0 in the related art. The charging may be started from a state where the voltage has a corresponding potential difference (a potential difference corresponding to the offset voltage of the MR head).

Therefore, the time required to charge the capacitor to the predetermined potential is relatively shortened, and consequently the transition period for switching from the idle state to the read state is shortened. Thereby, the same effect as in the above-described first embodiment of the present invention can be obtained. Further, according to the third aspect of the present invention, the first and second power supply lines having different voltages, the first power supply line, and the plurality of magnetic recording media are provided corresponding to each other, and the read state is provided. A plurality of Ms for reproducing signals from the corresponding magnetic recording media at the time of
One end of each of the R heads is connected to a plurality of connection lines connected via correspondingly provided resistors, and the other end of each of the plurality of MR heads is connected via a resistor. A plurality of first constant current sources respectively connected between the resistor and the second power supply line and supplying a sense current to the MR head in a read state when the corresponding MR head is selected; A collector provided for each of the plurality of MR heads, a collector connected to the first power supply line via a resistor,
A plurality of pairs of transistors respectively responding to voltage signals obtained from one end and the other end of the corresponding MR head, each emitter of each pair of transistors shared with the plurality of transistors, and the second power supply Second and third constant current sources respectively connected between the lines and supplying a constant current to a corresponding pair of transistors in a read state and when a corresponding MR head is selected; and the plurality of pairs of transistors. A capacitor connected between the emitters of each pair of transistors in a shared manner, and a fourth connected in parallel to the second and third constant current sources, respectively.
And turning on the fourth and fifth constant current sources for a predetermined time when a command to switch from one of the plurality of MR heads to another in the read state is issued. A signal reproducing circuit for an MR head, comprising:

According to the configuration based on the third embodiment, when the switching of the MR head is instructed in the read state, the control is performed such that the fourth and fifth constant current sources are turned on for a predetermined time. During this predetermined time, the pair of transistors constituting the read amplifier include the second and third transistors.
In addition to the original constant current by the constant current source of
Additional constant current flows from the constant current source. That is, similarly to the above-described first embodiment of the present invention, each emitter current of the read amplifier transistor temporarily increases, whereby the charge supplied to the capacitor temporarily increases.

Accordingly, the time required to charge the capacitor to a predetermined potential is relatively shortened, and consequently the transition period for switching the head in the read state is shortened. Thereby, effects similar to those of the first embodiment of the present invention can be obtained. The details of other structural features and operations of the present invention will be described using the embodiments described below with reference to the accompanying drawings.

[0023]

FIG. 1 shows a configuration of a signal reproducing circuit for an MR head according to a first embodiment of the present invention, and FIG. 2 shows an operation timing waveform thereof. In FIG.
The same reference numerals as those used in the configuration of the related art shown in FIG. 7 indicate the same components, and a description thereof will be omitted.

The feature of the MR head signal reproducing circuit according to the present embodiment is that the constant current source 13 and the constant current source 13 that supply the constant current Ib in parallel to the constant current sources 10 and 11 are different from the configuration of FIG. 14 and that a timing generation circuit 20 for controlling the on / off timing of the constant current sources 13 and 14 in response to the chip enable signal CE is provided.

The timing generation circuit 20 includes an inverter 21 responding to the chip enable signal CE, a delay circuit 22 for delaying the output of the inverter 21 for a predetermined time (a period indicated by td in FIG. 2), and a delay circuit 22
And an AND gate 23 for controlling on / off of the constant current sources 13 and 14 in response to the output SN and the chip enable signal CE. In this embodiment, the constant current sources 13 and 14 are turned on when the output of the AND gate 23 is at “H” level to supply the constant current Ib, and are turned off when the output of the AND gate 23 is at “L” level. Become.

In this configuration, when the chip enable signal CE is at "L" level (that is, when the chip is in an idle state), the constant current source 4 is off (in FIG. 2,
(Is = 0), and since the output of the AND gate 12 is at the “L” level, the constant current sources 10 and 11 are also turned off (Ia = 0 in FIG. 2). Since the output of the gate 23 is at the "L" level, the constant current sources 13 and 14 are also turned off (Ib = 0 in FIG. 2).

When the chip enable signal CE is set to "H" level in this state, the constant current source 4 is turned on to supply the constant current Is. At this time, the read / write control signal R
/ W is at the “H” level (read state), so that AND
The output of the gate 12 becomes "H" level, and the constant current source 10
And 11 are also turned on to supply the constant current Ia. Also,
At the time when the chip enable signal CE is set to the “H” level, the output SN of the delay circuit 22 of the timing generation circuit 20 is output.
Still maintain the previous state (ie, “H” level state). Therefore, the output of the AND gate 23 is "H".
Level, and the constant current sources 13 and 14 are also turned on to supply the constant current Ib.

After a lapse of a predetermined delay time (td) defined in the delay circuit 22, the output S of the delay circuit 22 is output.
N goes to the “L” level, and the AND gate 2
3 becomes “L” level, and the constant current sources 13 and 14
Are turned off. As described above, according to the configuration of the first embodiment, when switching from the idle state to the read state, the constant current sources 13 and 14 are controlled to be turned on for the predetermined time td. During this period, the emitters of the transistors 7 and 8 constituting the read amplifier are connected to the original constant current I
In addition to a, an additional constant current Ib from the constant current sources 13 and 14 flows. That is, the respective emitter currents of the transistors 7 and 8 are equal to the constant current I flowing during the original read state.
The current value is increased by Ib from a (Ia + I
b). As a result, the charge supplied to the capacitor 9 temporarily increases, and the capacitor 9 can be quickly charged to the predetermined potential V ₀ .

Therefore, the charging time of the capacitor 9 is determined by the conventional example (FIG. 7) which does not include the additional constant current sources 13 and 14.
As a result, the transition period for switching from the idle state to the read state is relatively short (the period indicated by tp2 in FIG. 2 is shorter than the transition period tp1 in the conventional example). Thus, the occurrence of a transient phenomenon (unnecessary offset voltage) during the transition period can be greatly suppressed. Further, since the period during which data can be read from the magnetic recording medium is lengthened by the shortened transition period, loss of data capacity can be minimized.

The “lead state” referred to in the embodiments of the present invention (including the first embodiment described above and the second and third embodiments described later) and the like is described in, for example, Japanese Patent Application Laid-Open No. 7-16900.
As disclosed in No. 9, "Read from a write state for reproducing (reading) data for the purpose of determining whether or not data written (written) in a write instruction has been properly recorded". It should be noted that "transition to state" has a different meaning. In this case, if a current is supplied to the MR head while data is being written, there is a possibility of destruction of the element. Therefore, do not supply a current to the MR head while data is being written. It is assumed.

"Read state" in the embodiment of the present invention
The expression includes other read modes (shown later) in addition to a normal read command (shown later). That is, the following two cases can be considered for performing the “switch from the idle state to the read state”. A case where a read command comes from an idle state where no command has come from the host device.

The MR head is kept on track on a predetermined track during an idle state in which no command is received from a higher-level device. The case where reading is performed to read servo information for the purpose of fixing the position). That is, in the embodiment of the present invention, the operation mode of the MR head is defined depending on whether the HDIC (head IC) is in the idle mode or the read mode.
In recent disk devices, there is a need to reduce power consumption in order to be built in a laptop personal computer or the like.

In an actual product, the bias of the MR head is always applied during the seek operation in the write mode or the read mode. (1) When a read instruction comes from the idle state (see above)
Consideration) Usually, even if no command is received from a higher-level device (such as a personal computer),
In order to keep the disk device in a command waiting state (in order to be able to immediately respond to a command), the spindle motor is rotated to bring the MR head into a state of waiting on a predetermined track (when the MR head is in a predetermined track). To monitor your location,
(The servo information is read with the aim of timing.) In this state, since the power is consumed, the use time of the battery-powered personal computer is limited. Therefore, if no command is received from the host device for a predetermined time, a low power consumption mode (also called a sleep mode) divided into several stages is set.

The sleep mode varies depending on the apparatus, but the head IC is turned off as the first step, the VCM (voice coil motor) is turned off as the second step, the spindle motor is turned off as the third step, and the other steps are turned as the fourth step. The circuit is turned off every time the monitoring time elapses by a procedure such as turning off the circuit. Therefore, in the sleep mode, since the head IC may be turned off, it may not be possible to respond immediately even if a read command is received. At that time,
The above-described method of the present invention is effective.

Of course, in the case of (2) described later, in addition to reading the servo after the idle state, when switching to the read mode when a read command comes and the seek operation is started,
It is similarly effective. (2) When servo information is read after idle state
(Considerations Regarding the Above) From another viewpoint, it has been recently found that the life of an MR head is shortened when a current is constantly flowing, and therefore, there is a tendency to keep the current from flowing as much as possible.

That is, even before the head IC is turned off in the sleep mode, no current is supplied to the MR head. Therefore, the present invention is not limited to the command for switching from the idle state to the read mode, and in the operation system using the MR head, there is a tendency that no current flows from the viewpoint of the life of the MR head. Is valid. (Because the MR head is used to read the servo information during the idle state and read the servo information during the write state, it should be noted that this is not a read command in this case.) During the seek operation, the head IC is in the read mode, and the MR head is always biased. However, when no command is issued for several minutes, servo information is read out, for example, every third servo information.

FIG. 3 shows an MR according to a second embodiment of the present invention.
FIG. 4 shows a configuration of a head signal reproducing circuit, and FIG. 4 shows an operation timing waveform thereof. 3, the same reference numerals as those used in the configuration of the related art shown in FIG. 7 represent the same components, and a description thereof will be omitted. The feature of the MR head signal reproducing circuit according to the present embodiment is that a dummy head circuit 30 for providing a prescribed potential difference VS between the terminals CX and CY of the capacitor 9 is provided in comparison with the configuration of FIG. And that a current setting circuit 40 is provided for the dummy head circuit 30 so that the potential difference VS can be adjusted from outside.

The dummy head circuit 30 simulates the structure of a signal reproducing circuit including the original MR head 1. That is, the dummy head circuit 30 includes the MR head 1
, A resistor 32 connected between one end of the resistor 31 and the power supply line V ₁ , and a resistor 33 connected to the other end of the resistor 31
Connected between the resistor 33 and the power supply line V ₂ ,
A current source 34 whose current value by the current setting circuit 40 is variable, each resistor 35 and 3 to the power supply line V ₁
6 are connected to each other via a resistor 6 and respond to voltage signals obtained from one end and the other end of the resistor 31, respectively.
It has a pair of transistors 37 and 38. The specified potential difference VS described above is taken out between the emitters of the transistors 37 and 38.

In the dummy head circuit 30, the current value of the current source 34 is set so as to supply the same current as the sense current Is supplied by the constant current source 4 in the original signal reproducing circuit including the MR head 1. ing. Therefore,
Resistor 3 having the same resistance value as the internal resistance of MR head 1
1 are ideally connected to the original MR in the read state.
The same voltage as the offset voltage appearing at both ends of the head 1 appears. Then, a potential difference VS corresponding to the offset voltage appears between the emitters of the transistors 37 and 38. In the present embodiment, the dummy head circuit 30 applies the potential difference VS to the capacitor 9 in the idle state (see the operation timing waveform diagram of FIG. 4).

As described above, according to the configuration of the second embodiment, the potential difference (V ₀ ≒ VS) corresponding to the offset voltage appearing at both ends of the MR head 1 in the read state is obtained by the operation of the dummy head circuit 30. Since the voltage is applied to the capacitor 9 during the idle state, the fluctuation of the voltage VC between the terminals of the capacitor 9 can be minimized when switching from the idle state to the read state. That is, when switching from the idle state to the read state, the capacitor 9
Is charged to a predetermined potential (VC = V ₀ in FIG. 4). In the related art (see FIG. 8), it is necessary to start charging from a state where the voltage VC between terminals of the capacitor is 0.
In this embodiment, the charging may be started from a state where the voltage VC between terminals of the capacitor has a corresponding potential difference (VS).

Accordingly, the time required to charge the capacitor 9 to a predetermined potential is greatly reduced, and as a result, the transition period for switching from the idle state to the read state is shortened (in FIG. 4, at tp3). The period shown is much shorter than the transition period tp1 in the conventional example). Thereby, the same effect as in the first embodiment (see FIGS. 1 and 2) can be obtained.

Also, ideally, in the read state, the MR
The same voltage as the offset voltage appearing at both ends of the head 1 should appear at both ends of the resistor 31 in the dummy head circuit 30, but they do not always match due to various factors. In such a case, by appropriately adjusting the current value of the current source 34 in the dummy head circuit 30 by the current setting circuit 40, the above-described effect can be reliably realized.

FIG. 5 shows an MR according to a third embodiment of the present invention.
FIG. 6 shows an operation timing waveform of the head signal reproducing circuit. In the present embodiment, a plurality of MR heads (in the illustrated example, two MR heads 1 and 5) are used.
An example of the configuration of a signal reproducing circuit provided with 1) is shown. In FIG. 5, the same reference numerals as those used in the configuration of the related art shown in FIG. 7 represent the same components, and the description thereof will be omitted.

The feature of the MR head signal reproducing circuit according to the present embodiment is that the constant current source 13 and the constant current source 13 for supplying the constant current Ib in parallel to the constant current sources 10 and 11 are different from the configuration of FIG. 14, the other head circuit 50 including the MR head 51 is provided, and one of the MR head 1 and the MR head 51 is selected in response to the head selection signal HS and the read / write control signal R / W. A selector 60 for outputting the head selection signals HS0 and HS1 for setting the state is provided, and the on / off timing of the constant current sources 13 and 14 is controlled in response to the head selection signals HS0 and HS1 output from the selector 60, respectively. That is, the timing generation circuit 20A is provided.

The other head circuit 50 includes an MR head 51,
A resistor 52 connected between one end of the MR head 51 and the power supply line V ₁ and the connection line 92; a resistor 53 connected to the other end of the MR head 51;
It is connected between the power supply line V _2, the head selection signal HS
A constant current source 54 whose on / off is controlled by 1;
Each collector is connected via a respective resistor 6 and 5 to the power supply line V _1, and a transistor 55 and 56 of the pair in response respectively to a voltage signal obtained from the one end and the other end of the MR head 51 ing. Transistor 55
And 56 are connected to the terminals CY and CX of the capacitor 9, respectively.

In the configuration of this embodiment, the selector 60
Indicates that when the read / write control signal R / W is at the "H" level (that is, the read state) and the head selection signal HS is at the "H" level, the head selection signal HS0 is set to the "H" level (the head selection signal HS1 is set to "H"). L "level) as the MR head 1
Is selected, the head selection signal HS1 is at the "H" level (the head selection signal HS0 is at the "L" level) in the same read state and the head selection signal HS is at the "L" level
To put the MR head 51 in the selected state. The constant current sources 13 and 14 are turned on when the output of the timing generation circuit 20A is at "H" level to supply the constant current Ib,
It turns off when the output of the timing generation circuit 20A is at "L" level. The timing generation circuit 20A outputs “H” when the head selection signal HS1 changes from “L” level to “H” level (that is, when the switching from the MR head 1 to the MR head 51 is instructed in the read state). It is configured to output a level signal. Therefore, at this time,
The constant current sources 13 and 14 are turned on, and the constant current I
b (see the operation timing waveform diagram of FIG. 6).

As described above, according to the configuration of the third embodiment, switching from the MR head 1 to the MR head 51 is performed in the read state (when the read / write control signal R / W is at the “H” level). The constant current source 13 for a predetermined time specified by the timing generation circuit 20A.
And 14 are turned on, so that during this predetermined time, the emitter currents of the transistors 7 and 8 are more than I.sub.a than the constant current Ia flowing during the original read state.
The current value is increased by b (Ia + Ib). As a result, the charge supplied to the capacitor 9 temporarily increases. On the other hand, during the transition period when the MR head is switched, the fluctuation of the voltage VC between terminals of the capacitor 9 can be minimized (V ₀ → V ₀ ′ in FIG. 6).

Therefore, the time required to charge the capacitor 9 to a predetermined potential can be greatly reduced, and as a result, the transition period during which the head is switched in the read state can be shortened (FIG. 9). 6 is tp4, which is much shorter than the transition period tp1 in the conventional example). Thereby, the same effect as in the first embodiment (see FIGS. 1 and 2) can be obtained.

Although the present invention has been described with reference to the first, second, and third embodiments, the present invention is not limited to these embodiments. For example, it is possible to appropriately combine the features of each embodiment, and such a combination is not shown, but will be easily conceived by those skilled in the art. Further, in the configuration example shown in the third embodiment (see FIG. 5), the case of two channels (that is, a signal reproducing circuit provided with two MR heads) has been described as an example. Of course, it is equally applicable.

[0050]

As described above, according to the present invention, M
In a magnetic recording / reproducing apparatus using an R head, when switching from the idle state to the read state or when switching the head in the read state, the transition period is shortened by shortening the charging time of the capacitor provided in the first-stage read amplifier. Therefore, it is possible to suppress the unnecessary offset component from being superimposed on the reproduction signal, thereby minimizing the loss of the data capacity.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a signal reproducing circuit for an MR head according to a first embodiment of the present invention.

FIG. 2 is an operation timing waveform diagram of the circuit of FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of a signal reproducing circuit for an MR head according to a second embodiment of the present invention.

FIG. 4 is an operation timing waveform diagram of the circuit of FIG. 3;

FIG. 5 is a circuit diagram showing a configuration of a signal reproducing circuit for an MR head according to a third embodiment of the present invention.

FIG. 6 is an operation timing waveform chart of the circuit of FIG. 5;

FIG. 7 is a circuit diagram showing a configuration of a conventional MR head signal reproducing circuit.

FIG. 8 is an operation timing waveform diagram of the circuit of FIG. 7;

[Explanation of symbols]

1,51 ... Magnetoresistance effect type (MR) head 2,3,5,6,31-33,35,36,52,53
... Resistor 4,10,11,13,14,34,54 ... Constant current source 7,8,37,38,55,56 ... N for read amplifier
PN transistor 9 ... capacitors 20, 20A ... timing generator 30 ... dummy head circuit 40 ... current setting circuit 50 ... other head circuit 60 ... selector 90 ... connecting line V _1, V ₂ ... power supply line (power supply voltage) Is, Is ₁ , Is ₂ ... constant current (sense current) flowing to MR head Ia, Ib ... constant current flowing to read amplifier transistor CE ... chip enable signal R / W ... read / write control signal HS, HS0, HS1 ... head selection signal

Claims (5)

[Claims] A first power supply line having a different voltage, a first power supply line, and one end of a magnetoresistive head for reproducing a signal from a magnetic recording medium in a read state;
A connection line connected via a resistor, connected to the other end of the magnetoresistive head via a resistor and connected between the resistor and the second power supply line, A first constant current source that sometimes supplies a sense current to the magnetoresistive head; and a collector connected to the first power supply line via a resistor, respectively, and one end of the magnetoresistive head and A pair of transistors respectively responsive to a voltage signal obtained from the other end; a pair of transistors connected between each emitter of the pair of transistors and the second power supply line, respectively; A second and a third constant current source for supplying a constant current, a capacitor connected between respective emitters of the pair of transistors, and a second and a third constant current source, respectively. Fourth and fifth constant current sources connected to a column, and controlling to turn on the fourth and fifth constant current sources for a predetermined time when switching from an idle state to a read state is commanded. And a signal reproducing circuit for a magnetoresistive head. 2. A first and a second power supply line having different voltages, the first power supply line and one end of a magnetoresistive head for reproducing a signal from a magnetic recording medium in a read state.
A connection line connected via a resistor, connected to the other end of the magnetoresistive head via a resistor and connected between the resistor and the second power supply line, A first constant current source that sometimes supplies a sense current to the magnetoresistive head; and a collector connected to the first power supply line via a resistor, respectively, and one end of the magnetoresistive head and A pair of transistors respectively responsive to a voltage signal obtained from the other end; a pair of transistors connected between each emitter of the pair of transistors and the second power supply line, respectively; Second and third constant current sources for supplying constant current, respectively, a capacitor connected between the emitters of the pair of transistors, and a lead connected to the capacitor when in an idle state. The magnetoresistive head magnetoresistive head signal reproducing circuit characterized by comprising a dummy head circuit for providing a potential difference corresponding to the offset voltage appearing across the time of state. 3. The signal reproducing circuit for a magnetoresistive head according to claim 2, further comprising means for externally adjusting a potential difference corresponding to the offset voltage with respect to the dummy head circuit. Characteristic signal reproducing circuit for magnetoresistive head. 4. The signal reproducing circuit for a magnetoresistive head according to claim 2, wherein the fourth and fifth constant current sources are connected in parallel to the second and third constant current sources, respectively.
A constant current source for controlling the fourth and fifth constant current sources to be turned on for a predetermined time when a command to switch from an idle state to a read state is issued. Signal reproducing circuit for effect type head. 5. A first and a second power supply line having different voltages, a first power supply line, and a plurality of magnetic recording media provided corresponding to each of the plurality of magnetic recording media, each of which corresponds to a read state. A plurality of connection lines each connected to one end of each of a plurality of magnetoresistive heads for reproducing signals from a corresponding one of the plurality of magnetoresistive heads; Are connected to each other via a resistor and connected between the resistor and the second power supply line, respectively. When the corresponding magnetoresistive head is selected in a read state and the corresponding magnetoresistive head is selected, A plurality of first sensors for supplying a sense current to the effect type head.
A plurality of constant current sources, each of the plurality of magnetoresistive heads being provided corresponding to each of the plurality of magnetoresistive heads, each collector connected to the first power supply line via a resistor, respectively, A plurality of pairs of transistors respectively responding to the voltage signals obtained from one end and the other end of the pair, and between each emitter of each pair of transistors and the second power supply line in a form shared by the plurality of pairs of transistors. Second and third constant current sources respectively connected and supplying a constant current to a corresponding pair of transistors when a corresponding magnetoresistive head is selected in a read state and the corresponding pair of transistors; A capacitor connected between the emitters of each pair of transistors in a shared manner; and a fourth connected in parallel to the second and third constant current sources, respectively. And a fifth constant current source, and when the switching from one of the plurality of magnetoresistive heads to another is commanded in the read state, the fourth and fifth constant current sources are switched for a predetermined time. A signal reproducing circuit for a magnetoresistive head, comprising: a circuit for controlling the signal to be turned on.