JPH05308276A - Ecl gate - Google Patents

Abstract

PURPOSE:To reduce the power consumption and to quicken the transmission speed of an output signal of the gate. CONSTITUTION:A differential amplifier circuit is connected between emitters of transistors(TRs) Q3, Q4 and a low potential side power supply line VEE in an emitter follower circuit 30 and bases of a couple of TRs Q5, Q6 of the differential amplifier circuit are connected to bases of a couple of TRs Q1, Q2 of a current switch circuit 10. In the case of voltage VI>reference voltage VR, the TRQ3 is turned off, the TRQ4 is turned on, the TRQ5 is turned on and the TRQ6 is turned off, a potential on an output signal line X goes to a low level at a high speed and a potential of an output signal line Y goes to a high level at a high speed. Since the emitter follower circuit 30 is provided with only one constant current source, power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to ECL gates.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional ECL gate.

The ECL gate comprises a current switch circuit 10 and an emitter follower circuit 20 for amplifying the drive capability of the output of the current switch circuit 10.

The current switch circuit 10 includes a pair of NPs.
The emitters of the N-type transistors Q1 and Q2 are both connected to the input end of the constant current source 11, the output end of the constant current source 11 is connected to the low potential side power supply line VEE, and the collectors of the NPN-type transistors Q1 and Q2 are respectively connected. Resistors R1 and R
It is connected to the high potential side power supply line GND via 2.

In the emitter follower circuit 20, the base, collector and emitter of the NPN transistor Q3 are connected to the collector of the NPN transistor Q1, the high potential side power supply line GND and one end of the circuit element 21, respectively, and NP
The base, collector and emitter of the N-type transistor Q4 are connected to the collector of the NPN-type transistor Q2, the high potential side power supply line GND and one end of the circuit element 22, respectively, and the other ends of both the circuit elements 21 and 22 are the low potential side power source. It is connected to the supply line VEE.

The input terminal of the ECL gate is the base of the NPN transistor Q1, and the non-inverting output terminal and the inverting output terminal are the emitters of the NPN transistors Q3 and Q4, respectively. Further, the fixed reference voltage VR or the voltage * VI which is the inverted level of the input voltage VI is applied to the base of the NPN transistor Q2. Circuit elements 21 and 2
2 uses the resistor R1 or the constant current source 11.

The NPN type transistors Q3 and Q4 have emitters connected to other ICs via output signal lines X and Y, respectively.
Consider that the output signal lines X and Y are connected to the input ends of a circuit having a relatively large fan-in and the wiring capacitance of the output signal lines X and Y is relatively large.

In the above structure, if VI> VR,
The base potential of the NPN transistor Q3 drops and NP
The base potential of the N-type transistor Q4 rises, and the NPN
Type transistor Q3 is off, NPN type transistor Q4
Turns on. Therefore, the output voltage * VO becomes low level and the output voltage VO becomes high level.

[0009]

In this case, regarding the output signal line X, when a resistor is used as the circuit element 21,
The time constant is represented by the product of the wiring capacitance of the output signal line X and the resistance value of the circuit element 21, and the electric charge is discharged to the low potential side power supply line VEE side through the output signal line X and the circuit element 21. , It becomes slow that the potential of the output signal line X becomes low level. If the resistance value of the circuit element 21 is reduced to increase the speed, the power consumption of the circuit element 21 increases. Also,
When a constant current source is used as the circuit elements 21 and 22, the potential of the output signal line X quickly becomes a low level, but since two constant current sources are used, the power consumption thereof becomes large.

The output signal line Y is similar to the output signal line X.

In view of the above problems, it is an object of the present invention to provide an ECL gate which can reduce power consumption and increase the transmission speed of an output signal.

[0012]

FIG. 1 shows the principle configuration of an ECL gate according to the present invention.

In this ECL gate, the emitters of the first and second transistors Q1 and Q2 are commonly used by the first constant current source 1
1 is connected to the low-potential-side power supply line VEE via
And the collectors of the second transistors Q1 and Q2 are connected to the high potential side power supply line GND through the first and second resistors R1 and R2, respectively.
And the bases of the third and fourth transistors Q3 and Q4 are connected to the collectors of the first and second transistors Q1 and Q2, respectively, and the third and fourth transistors Q3 and Q4 are connected.
The collectors of 4 are both connected to the high potential side power supply line GND, and the emitters of the fifth and sixth transistors Q5 and Q6 are commonly connected to the low potential side power supply line VEE via the second constant current source 31. , Fifth and sixth transistors Q5,
The collector of Q6 includes an emitter follower circuit 30 connected to the emitters of the third and fourth transistors Q3 and Q4, respectively.

The operation of the above configuration will be described for the case of VI> VR.

If VI> VR, the third transistor Q
The base potential of the third transistor Q3 is turned off, the base potential of the fourth transistor Q4 is raised, and the base potential of the third transistor Q3 is turned off.
The transistor Q4 is turned on. Further, the fifth transistor Q5 is turned on and the sixth transistor Q6 is turned off. Therefore, the output voltage * VO transits to the low level and the output voltage VO transits to the high level.

The charges flowing through the output signal line X are discharged to the low potential side power supply line VEE side through the fifth transistor Q5 and the second constant current source 31. At this time, the current is drawn by the second constant current source 31 and the third transistor Q3.
Is off, the potential of the output signal line X quickly becomes low level. Also, the fourth transistor Q4 is turned on,
Since the sixth transistor Q6 is off, the charges move from the high potential side power supply line GND to the outside through the fourth transistor Q4 and the output signal line Y at high speed, and the potential of the output signal line Y becomes high level at high speed. Become.

Also in the case of VI <VR, the same effects as above can be obtained.

Moreover, since the emitter follower circuit 30 uses only one constant current source, the emitter follower circuit 3
The power consumption at 0 is half that in the case of FIG.

In the first mode of the present invention, as shown in FIG. 2, for example, the third resistor R3 is connected between the emitters of the third and fourth transistors Q3 and Q4.

When VI> VR, the resistor R3 increases the current flowing through the fourth transistor Q4 to increase the switching speed of the fourth transistor Q4 and speed up the output signal line Y to a high level. When VI <VR, the current flowing through the third transistor Q3 is increased, the switching speed of the third transistor Q3 is increased, and the output signal line X becomes high in speed.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 2 shows the EC of the first embodiment.
The circuit of L gate is shown. The same components as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

Constant current source 11 of current switch circuit 10
Is such that the emitter of the NPN transistor Q7 is connected to one end of the resistor R4, the constant voltage VC is applied to the base of the NPN transistor Q7, and the collector of the NPN transistor Q7 and the other end of the resistor R4 are input to the constant current source 11. It is the end and the output end.

In the emitter follower circuit 30A, the emitters of NPN transistors Q3 and Q4 are connected to the collectors of NPN transistors Q5 and Q6, respectively, and NP
The emitters of the N-type transistors Q5 and Q6 are both connected to the input terminal of the constant current source 31. The constant current source 31 has the same configuration as the constant current source 11 and includes an NPN transistor Q8.
Is connected to one end of a resistor R5, a constant voltage VC is applied to the base of an NPN transistor Q8,
The collector of the type transistor Q8 and the other end of the resistor R5 serve as an input end and an output end of the constant current source 31. The output terminal of the constant current source 31 is connected to the low potential side power supply line VEE. The bases of the NPN type transistors Q5 and Q6 are connected to the bases of the NPN type transistors Q1 and Q2, respectively. A resistor R3 for increasing the current driving capability is connected between the emitter of the NPN type transistor Q3 and the emitter of the NPN type transistor Q4. The resistance value of the resistor R3 is relatively large, and for example, a resistor of several tens KΩ is used.

At the input stage of the current switch circuit 10,
Input buffer circuits 41 and 42 are connected to the NPN transistor Q1 side and the Q2 side, respectively. In the input buffer circuit 41, the emitter of the NPN transistor Q9 is connected to the base of the NPN transistor Q1 and one end of the resistor R6, the collector of the NPN transistor Q9 is connected to the high potential side power supply line GND, and the other resistor R6 is connected. The end is connected to the low potential side power supply line VEE. Similarly, the input buffer circuit 42 includes an NPN transistor Q10.
Of the NPN transistor Q2 is connected to the base of the NPN transistor Q2 and one end of the resistor R7.
Is connected to the high potential side power supply line GND, and the other end of the resistor R7 is connected to the low potential side power supply line VEE. The input voltage VI is applied to the base of the NPN transistor Q9, and the fixed reference voltage VR or the voltage * VI obtained by inverting the level of the input voltage VI is applied to the base of the NPN transistor Q10. Input buffer circuit 41
Reference numerals 42 and 42 denote the input voltage VI and the reference voltage VR, respectively, of the base-emitter voltage VBE of the NPN transistor.
NPN transistor Q1
This is to prevent the base potentials of Q2 and Q2 from becoming higher than the collector potential and the NPN transistors Q1 and Q2 to be saturated.

Next, the operation of the first embodiment configured as described above will be described in the case where VI> VR.

When VI> VR, the base potential of the NPN transistor Q3 decreases, and the NPN transistor Q3
4, the base potential of the NPN transistor Q3 increases.
Turns off and the NPN transistor Q4 turns on. Further, the NPN type transistor Q5 is turned on and the NPN type transistor Q6 is turned off. Therefore, the output voltage * VO
Shifts to a low level, and the output voltage VO shifts to a high level.

The charge flowing through the output signal line X is N
It is discharged to the low potential side power supply line VEE side through the PN type transistor Q5 and the constant current source 31. At this time, the current is drawn by the constant current source 31 and the NPN transistor Q3.
Is off, the potential of the output signal line X quickly becomes low level. Further, since the NPN transistor Q4 is on and the NPN transistor Q6 is off, the charge moves from the high potential side power supply line GND to the outside through the NPN transistor Q4 and the output signal line Y at high speed, and the output signal line The potential of Y becomes high level at high speed.

Moreover, since the emitter follower circuit 30A uses only one constant current source, the power consumption is half that in the case of FIG.

The resistor R3 increases the current flowing through the NPN type transistor Q4, increases the switching speed of the NPN type transistor Q4, and speeds up the output signal line Y to a high level.

[Second Embodiment] FIG. 3 shows an EC of the second embodiment.
The circuit of L gate is shown. The same components as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

In this ECL gate, the emitter of the NPN transistor Q9 of the input buffer circuit 41A and the NPN are connected.
Diode D1 between the base of the transistor Q1
Is connected in the order of the anode and the cathode, and similarly, the diode D2 is connected in the order of the anode and the cathode between the emitter of the NPN type transistor Q10 of the input buffer circuit 42A and the base of the NPN type transistor Q2.

As a result, the input voltage VI and the reference voltage V
R is the base-emitter voltage V of the NPN transistor
Since the voltage between the terminals of BE and the diode drops, NP
Since the base potentials of the N-type transistors Q1 and Q2 are higher than the collector potential, the NPN-type transistors Q1 and Q2
2 can be prevented from becoming saturated.

The other points are the same as in FIG.

[0035]

As described above, the ECL according to the present invention
The gate has an excellent effect that the power consumption can be reduced and the transmission speed of the output signal can be increased.

Further, according to the first aspect of the present invention, there is an effect that the transmission speed of the output signal can be further increased.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of an ECL gate according to the present invention.

FIG. 2 is a circuit diagram of an ECL gate according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of an ECL gate according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional ECL gate.

[Explanation of symbols]

 10 Current switch circuit 11, 31 Constant current source 20, 30, 30A Emitter follower circuit 41, 41A, 42, 42A Input buffer circuit Q1 to Q10 NPN type transistor R1 to R7 Resistance D1 and D2 Diode VI, * VI Input voltage VO, * VO Output voltage VR Reference voltage X, Y Output signal line GND High potential side power supply line VEE Low potential side power supply line

Claims (2)

[Claims] 1. A first and a second transistor (Q1, Q)
The emitter of 2) is commonly connected to the low potential side power supply line (VEE) via the first constant current source (11), and the collectors of the first and second transistors are respectively the first and second
Through the resistors (R1, R2) of the high potential side power supply line (G
ND) connected to the current switch circuit (10) and the bases of the third and fourth transistors (Q3, Q4) are connected to the collectors of the first and second transistors, respectively. The collectors of the transistors are connected to the high-potential-side power supply line, and the emitters of the fifth and sixth transistors (Q5, Q6) are commonly connected to the low-potential-side power supply via the second constant current source (31). An ECL gate comprising: an emitter follower circuit (30) connected to a supply line, the collectors of the fifth and sixth transistors being connected to the emitters of the third and fourth transistors, respectively. 2. The third and fourth transistors (Q
3. An ECL gate according to claim 1, characterized in that a third resistor (R3) is connected between the emitters of Q3 and Q4.