JPH02188025A - Line driver - Google Patents

Abstract

PURPOSE:To improve and reduce frequency characteristics by constituting 1st, 2nd, and 3rd transistors(TR) which constitute differential couples, and 4th and 5th TRs connected to the collectors of the 2nd and 3rd TRs by using only npn TRs. CONSTITUTION:When base potentials VM, VL, and VH are logically L, L, and H respectively, a TR 2 turns on and TRs 1 and 3 turn off. Further, a current I0 flows to the TR 2. The output levels of inverters 14 and 12 are logically L and H, so the current I0 is obtained from a power source Vcc through the primary winding 6 of a line transformer L. When the base potentials VM, VL, and VH are logically L, H, and L, the current 10 flows to the TR 3. Then the current 10 flows from the power source Vcc through the primary winding 6 of the line transformer L. The frequency characteristics are therefore improved and the absolute value of the current amplification factor beta of the npn TR is large, so its variance causes no problem.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a line driver, and in particular to an ISDN (Integrated
5services Digital Network
).

(Prior Art) A conventional line driver for I5DN is shown in FIG. The operation will be described below with reference to the same figure.

First, base potentials vM, vL, and V□ of transistors Q2 and Q3 are logically low level (hereinafter abbreviated as rLJ), L, and high level (hereinafter rLJ), respectively.
It is abbreviated as HJ. ), only transistor Q3 of the differential pair consisting of transistors Q1, Q2 and Q3 is conductive. Due to conduction of transistor Q3, transistor Q
4, Q6, and Q7 are sequentially turned on, and current flows from the power supply VCC to the ground point GND through the transistors Q4 and Q6. Furthermore, transistor Q7 sinks current due to the action of a current mirror. On the other hand, transistor Q9 is non-conductive and no current flows through it, but a portion of the current that transistor Q7 sinks flows through transistor Q8. Furthermore, most of the current that is absorbed by transistor Q7 flows through transistor Q5. The current ratio between the transistor Q5 and the transistor Q8 changes depending on the line transformer L as a load, and as a result, a current ILI flows through the primary side of the line transformer L.

Next, when the base potentials VM, VL, and V are logically H, L, and L, respectively, the transistor Q1 becomes conductive, and the transistors Q2 and Q3 become nonconductive. Therefore,
Since the transistors Q4 and Q are non-conductive, no current flows to the primary side of the line transformer L.

Finally, when base potentials VM, V, and V□ are logically H and L, respectively, only transistor Q2 is conductive. In this case, the base potential V
M s V L and vH are logically each, and L
and H.

Specifically, the conduction of the transistor Q9 causes the transistors Q1 and Qto to conduct, and a current flows from the power supply VCC to the ground point GND through the transistors Q9 and Qll. Also, due to the action of the current mirror, the transistor Q
1o sucks current.

Therefore, on the primary side of the line transformer L, the initial current IL
A current IL2 flows in the same amount as I but in the opposite direction.

As a result, the load RL on the secondary side of the line transformer L has a three-value logic waveform as shown in FIG.

However, such a circuit has the following drawbacks.

Since the transistors Q4 and Q9 are pnp type transistors, they have poor frequency characteristics and cannot operate at high speed. Also,
Transistors Q4 and Q9 due to variations in current amplification factor β of transistors Q4 and Q9, and due to temperature changes.
Fluctuations in the base-emitter voltage VBH cause variations and fluctuations in the current flowing therethrough. Therefore, variations and fluctuations in these currents result in changes in the output amplitude, and l5
This is inconvenient as it may deviate from the DN standard. (An example of such a circuit is the 1986 IEICE Comprehensive National Conference.) A study of driver circuits in the 15DN user/network interface.

There are pages 9-42. ) (Problem to be solved by the invention) As described above, in the past, PNP transistors were used in circuit configurations, which resulted in poor frequency characteristics, and variations and fluctuations in the current of these transistors caused the amplitude of the output to change. There was a drawback that it was a change and deviated from the 15DN standard.

Therefore, an object of the present invention is to provide a line driver that can improve frequency characteristics and prevent fluctuations in V[lH due to variations in output current and temperature changes.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the line driver of the present invention includes a first line driver whose emitters are connected in common and which constitutes a differential pair.
second and third npn transistors, a common constant current source of the differential pair connected to their connection point, and an emitter connected to the collector of the second transistor and one end of the primary winding of the line transformer. a fifth npn transistor whose emitter is connected to the collector of the third transistor and the other end of the primary winding of the line transformer; and a fifth npn transistor whose emitter is connected to the base of the first transistor. the fourth input terminal via the base of the second transistor and the first inverter.
a second input terminal connected to the base of the fifth transistor; a third input terminal connected to the base of the fifth transistor via the third transistor base and a second inverter; It has a first potential supply source connected to the collectors of the first, fourth, and fifth transistors, and a second potential supply source connected to the common constant current source.

Further, by applying a logic signal to the first, second, and third input terminals, the logic level is set to a high level;
An output corresponding to a low level or an intermediate level can be obtained via a line transformer.

Furthermore, the logic signal applied to the first input terminal may always be at a constant potential, and this may correspond to an intermediate level of the three-value logic level.

(Function) According to such a circuit configuration, improvement in frequency characteristics can be achieved by using only npn type transistors. Further, variations in the output current of the transistors and current changes due to temperature changes are also reduced.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a line driver of the present invention. np
N-type transistors 1, 2 and 3 constitute a differential pair, the operating current of which is determined by a constant current source 4 commonly connected to the emitters of transistors 1, 2 and 3. The collector of the transistor 2 is connected to the emitter of the npn transistor 5, and its connection point is connected to one end of the primary winding 6 of the line transformer L. transistor 3
The collector of is connected to the emitter of the npn transistor 7, and its connection point is connected to the other end of the primary winding B of the line transformer L. Secondary winding 8 of line transformer L
A resistor 9 as a so-called dummy load, which simulates a line and a terminal connected to the line, is connected to the line. and,
An input terminal 10 is connected to the base of transistor l. Further, the input terminal 11 is connected to the base of the transistor 3 and the base of the transistor 7 via the inverter 12. Further, an input terminal 13 is connected to the base of the transistor 2 and to the base of the transistor 5 via an inverter 14. Transistor 1.
The collectors of 5 and 7 are connected to the voltage 11Vcc. The other end of the constant current [4 is connected to the ground point GND.

The inverters 12 and 14 may have a bipolar structure or a CMO8 structure, but they must operate at high speed. For example, an inverter with npn transistor stages is sufficient. Further, transistors 5 and 7 are driven by inverters 14 and 12, respectively, and operate as emitter followers.

Further, vM, V and VII are applied to the bases of input terminals 1O111 and 13, respectively, as logic signals corresponding to the three-value logic level of the output.

Next, the operation of the line driver will be explained with reference to the same figure. In addition, transistor! , 2 and 3 are assumed to be vMlVL and vH, respectively.

First, when the base potentials vM%vL and vH are logically L, L, and H, respectively, transistor 2 is turned on and transistors 1 and 3 are turned off. Therefore, current io flows through transistor 2.

On the other hand, since the output levels of inverters 14 and 12 are logically L and H, respectively, transistor 5 is off;
Transistor 7 is turned on. Therefore, the current 1o that the transistor 2 sinks is obtained from the primary winding B of the line transformer L via the transistor 7 from the power supply VCC. That is, this current I. becomes the current lL flowing through the primary winding 6 of the line transformer L.

Next, the base potentials vM, ■L and V. are logically H, L, and L, respectively, transistor I is turned on and transistors 2 and 3 are turned off.

Therefore, since the current IO flows from the power supply VCC to the ground point GND via the transistor 1, no current flows to the primary winding 6 of the line transformer L.

Finally, the base potentials V M s V L and V. If they are logically LSI and L, respectively, transistor 3 is turned on and transistors 1 and 2 are turned off. Therefore,
Current IO flows through transistor 3.

On the other hand, since the output levels of inverters 14 and 12 are logically H and L, respectively, transistor 5 is on;
Transistor 7 is turned off. Therefore, the current that transistor 3 sinks! 0 is the power supply Vt? C is obtained from the primary winding B of the line transformer L via the transistor 5. That is, the current IL flowing through the primary winding 6 of the line transformer L is the same amount of current IO as in the first case,
The current flows in the opposite direction.

As a result, the load RL on the secondary side of the line transformer L is
A ternary logic waveform as shown in FIG. 4, similar to the conventional one, is obtained.

FIG. 2 shows inverters 14 and 1 of the line driver.
This is a concrete realization of 2. This will be explained below with reference to the same figure.

The inverters 14 and 12 are composed of npn type) transistors IB and 17, respectively, and achieve high speed circuit operation. npn type transistor 1B.

17 and 18 constitute a differential pair, the operating current of which is determined by a constant current source 19 commonly connected to the emitters of transistors 18.17 and 18. The other end of the constant current source 19 is connected to a ground point GND. transistor 1
The collectors of B and 17 are connected to the power supply VCC via resistors 20 and 21, respectively. Note that the bases of the transistors 16 and 17 serve as inputs, and the collectors serve as outputs. Further, a constant voltage source 22 is connected to the base of the transistor 18.

By the way, in the line driver, a constant potential can always be applied to the base of the transistor 1, and this can be made to correspond to the intermediate level of the output. In this case, logic signals corresponding to the high level or low level of the output three-value logic level may be applied to the bases of transistors 2 and 3, respectively.

[Effects of the Invention] As described above, the line driver of the present invention provides the following effects.

Since all of the circuits are composed of npn type transistors, the high speed performance is not impaired and the frequency characteristics can be improved. Also, the current amplification factor β of the npn transistor
Since the absolute value of is high, its variation does not pose a problem. Furthermore, each transistor, which is essentially a switch, has no temperature characteristics.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a line driver according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the inverter in FIG. 1, and FIG. 3 is a circuit diagram showing a conventional line driver. FIG. 4 is a timing diagram showing the operation of the line driver shown in FIG. 3. 1-3. 5. 7... npn type transistor, 4...
...Constant current source, 12.14...Inverter, G...
- Secondary winding, 8...Secondary winding, 9...Resistance, 10.1
1.13...Input terminal, VCC...? 8 source, GND
...Grounding point. Applicant's agent Patent attorney Takehiko Suzue Figure 3

Claims (3)

[Claims] (1) In a line driver that drives a line via a line transformer, first, second, and third npn transistors whose emitters are commonly connected and constitute a differential pair, and the a common constant current source of a differential pair; a fourth npn type transistor whose emitter is connected to the collector of the second transistor and one end of the primary winding of the line transformer; and a fourth npn type transistor whose emitter is connected to the collector of the third transistor and a fifth npn transistor connected to the other end of the primary winding of the line transformer; a first input terminal connected to the base of the first transistor; a second input terminal connected to the base of the fourth transistor via an inverter; and a second input terminal connected to the base of the third transistor and the base of the fifth transistor via a second inverter. 3 input terminals, and the first,
a first potential supply source connected to the collectors of the fourth and fifth transistors; and a second potential supply source connected to the common constant current source.
A line driver comprising: a potential supply source. (2) A logic signal corresponding to an output logic level of a high level, a low level, or an intermediate level is applied to the first, second, and third input terminals.
Line driver listed. (3) Applying a constant potential to the first input terminal whose output logic level corresponds to an intermediate level;
2. The line driver according to claim 1, wherein a logic signal corresponding to an output logic level of high level or low level is applied to the input terminal of the line driver.