JPS6123415A - Ecl-ttl level converting circuit - Google Patents

Ecl-ttl level converting circuit

Info

Publication number
JPS6123415A
JPS6123415A JP59143709A JP14370984A JPS6123415A JP S6123415 A JPS6123415 A JP S6123415A JP 59143709 A JP59143709 A JP 59143709A JP 14370984 A JP14370984 A JP 14370984A JP S6123415 A JPS6123415 A JP S6123415A
Authority
JP
Japan
Prior art keywords
output
transistor
current
emitter
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59143709A
Other languages
Japanese (ja)
Inventor
Hiroshi Mabuchi
馬渕 浩
Seigo Naito
内藤 清吾
Toshiji Tamura
田村 年司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP59143709A priority Critical patent/JPS6123415A/en
Publication of JPS6123415A publication Critical patent/JPS6123415A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain an output waveform without dependancy of a power supply voltage by holding a base current when an output transistor (Tr) is turned on to a constant value even if the power supply voltage is fluctuated. CONSTITUTION:A common emitter is brought into a constant voltage by inputting an output of emitter follower Trs Q3, Q6 receiving an operating output of an emitter coupling logical circuit comprising Trs Q1, Q2 to each base of Tr pairs Q7, Q8. The said constant voltage and a constant current circuit comprising Trs Q9, Q10 of diode connection are used to bias a TrQ11. A base current IB when the output TrQ5 is turned on is obtained from the difference between current I1 and I2, where I1 is a current flowing to the resistor R5 at input H level and I2 is a collector current of the TrQ11 and the relation of IB=VBE/R9 is obtained and the circuit is immune to the effect of a power supply voltage. Thus, even if the power supply voltage is fluctuated, the depth of the saturation of the TrQ5 is kept constant and a stable output waveform is obtained.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、バイポーラトランジスタを使用したECL−
TTLレベル変換回路、特に電源電圧に依存することな
く、安定な出力が可能なECL−TTLレベル変換回路
に係わるものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an ECL-CL using bipolar transistors.
The present invention relates to a TTL level conversion circuit, particularly an ECL-TTL level conversion circuit that is capable of stable output without depending on power supply voltage.

[従来の技術] 従来のECL−TTLレベル変換回路の一例を第2図に
示す。
[Prior Art] An example of a conventional ECL-TTL level conversion circuit is shown in FIG.

トランジスタ対Q 1Q2からなるエミッタ結金形論理
回路は定電流源I。で駆動され、出力信号はエミッタホ
ロワQ3を介し、ダイオードでレベルシフトしてTTL
レベル変換回路に入力される。
The emitter-coupled logic circuit consisting of the transistor pair Q1Q2 is a constant current source I. The output signal is level-shifted by a diode through the emitter follower Q3, and the output signal is TTL-driven.
Input to the level conversion circuit.

TTLレベル変換回路は、トランジスタQ4、抵抗R1
R6、出力用トランジスタQ からなす、抵抗R5、R
6で分割された信号により、出力用トランジスタQ5を
駆動する。
The TTL level conversion circuit includes a transistor Q4 and a resistor R1.
Resistors R5 and R made up of R6 and output transistor Q
The output transistor Q5 is driven by the signal divided by 6.

かかる回路は入力端子INの゛H″レベルまたは“L”
レベルに応じ、出力用トランジスタQ5を“ON”また
は“OF F ”させ、TTLレベルに変換した出力を
得ることができる。
Such a circuit operates when the input terminal IN is at the “H” level or “L” level.
Depending on the level, the output transistor Q5 is turned "ON" or "OFF" to obtain an output converted to a TTL level.

[発明が解決しようとする問題点] ここで、出ツノ用トランジスタQ5が110 N I+
の時のベース電流IBは、入力11 HITレベル時の
抵抗Rを流れる電流■1′と抵抗R6を流れる電流■2
の差で表わされ次式となる。
[Problem to be solved by the invention] Here, the output transistor Q5 is 110 N I+
The base current IB at the time of input 11 is the current ■1' flowing through the resistor R at the HIT level and the current ■2 flowing through the resistor R6.
It is expressed as the difference between

1  =T’  −’l   ” −(V  −RI  −3V、E) /R5C10 −V 8./ R6 尚、■ は定電流の電流、R1、R5、R6は抵抗R、
R5、R6の抵抗値、 Vccは電源電圧、VB[はト
ランジスタのベース・エミッタ間電圧である。
1 = T'−'l ” −(V −RI −3V, E) /R5C10 −V 8./R6 In addition, ■ is the constant current, R1, R5, and R6 are the resistors R,
The resistance values of R5 and R6, Vcc is the power supply voltage, and VB[ is the voltage between the base and emitter of the transistor.

上式よりも明らかなように、ベース電流I8は電源電圧
vccに依存性を持っている。
As is clear from the above equation, the base current I8 has dependence on the power supply voltage vcc.

従って、電源電圧が変動すると出力用トランジスタQ5
の飽和の深さが変わり、出力波形も変化するという問題
があった。
Therefore, when the power supply voltage fluctuates, the output transistor Q5
There was a problem in that the depth of saturation changes and the output waveform also changes.

[問題点を解決するための手段] 本発明の目的は、前記した従来技術の欠点を解消し、出
力波形が電源電圧によって変化しないFCL−TTLレ
ベル変換回路を提供することにある。
[Means for Solving the Problems] An object of the present invention is to eliminate the drawbacks of the prior art described above and to provide an FCL-TTL level conversion circuit whose output waveform does not change depending on the power supply voltage.

即ちその要旨とするところは、エミッタを共通とするト
ランジスタ対からなる電流切換形論理回路の出力をTT
Lレベルに変換する回路において、上記トランジスタ対
各々の出力に接続されたエミッタホロワの出力を、コレ
クタ・エミッタ共通のトランジスタ対のベースに各々入
力し、該トランジスタ対の共通エミッタに抵抗、ダイオ
ードを順次接続して定電流回路を形成し、また、前記エ
ミッタホロワの一方の出力に接続するトランジスタのエ
ミッタに抵抗を接続し、該抵抗の他端に出力用トランジ
スタのベース及び前記定電流回路によりバイアスされた
トランジスタのコレクタを接続して構成されたことを特
徴とするECL−TTLレベル変換回路にある。
That is, the gist is that the output of a current switching type logic circuit consisting of a pair of transistors having a common emitter is
In the circuit for converting to L level, the outputs of the emitter followers connected to the outputs of each of the above transistor pairs are input to the bases of the collector-emitter common transistor pairs, and a resistor and a diode are sequentially connected to the common emitters of the transistor pairs. A resistor is connected to the emitter of a transistor connected to one output of the emitter follower, and the other end of the resistor is connected to the base of an output transistor and a transistor biased by the constant current circuit. The ECL-TTL level conversion circuit is characterized in that it is configured by connecting the collectors of the ECL-TTL level converter.

[実施例] 第1図は本発明ECL−TTLレベル変換回路の一実施
例を示すもので、第2図と同一部分は同じ符号で示し、
ここでは説明を省略する。
[Embodiment] FIG. 1 shows an embodiment of the ECL-TTL level conversion circuit of the present invention, and the same parts as in FIG. 2 are designated by the same reference numerals.
The explanation will be omitted here.

まずトランジス、りQl、Q2からなるエミッタ結合形
論理回路の作動出力を受けるエミッタホロワQ 1Q6
の出力を、トランジスタ対Q7、0.8の各々のベース
に入力することにより、その共通エミッタを定電圧にす
る。
First, an emitter follower Q1Q6 receives the operational output of an emitter-coupled logic circuit consisting of transistors Ql and Q2.
By inputting the output of Q7 to the base of each of the transistor pair Q7, 0.8, their common emitters are made to have a constant voltage.

つぎにこの定電圧及び抵抗R9、ダイオード接続のトラ
ンジスタQ9 ” 10により定電流回路を構成してト
ランジスタQ11をバイ4アスすると、トランジスタQ
11のコレクタ電流12′は次式となる。
Next, a constant current circuit is constructed with this constant voltage, resistor R9, and diode-connected transistor Q9''10, and transistor Q11 is biased.
The collector current 12' of No. 11 is expressed by the following equation.

12= = (Vo、、−R,I o−4V2C) /
R9・(1)一方、入力11 HIIレベルの時に抵抗
R5を流れる電流11は次式となる。 。
12= = (Vo,,-R,I o-4V2C) /
R9·(1) On the other hand, the current 11 flowing through the resistor R5 when the input 11 is at HII level is given by the following equation. .

1l−(VoC−R1Io−3■8F)/R5・・・(
2)ここで、出力用トランジスタQ5が“” ON ”
時のベース電流■8は、抵抗R5を流れる電流11とト
ランジスタQ11のコレクタ電流■2の差で表わされる
ため、(1)、(2式より次式となる。
1l-(VoC-R1Io-3■8F)/R5...(
2) Here, the output transistor Q5 is “ON”.
Since the base current (2)8 at the time is expressed by the difference between the current 11 flowing through the resistor R5 and the collector current (2) of the transistor Q11, the following equation is obtained from equations (1) and (2).

■8−11−■2′ = (1/R5−1/R9)(V、o−RoI。■8-11-■2' = (1/R5-1/R9) (V, o-RoI.

−3V  )十V8E/R9 B[ 今、抵抗R5とR9の抵抗値を等しくすると、■ −■
8E/R9となり、電源電圧の影響を受けなくなる。
-3V) 10V8E/R9 B[ Now, if the resistance values of resistors R5 and R9 are made equal, ■ -■
8E/R9, and is not affected by the power supply voltage.

従って、電源電圧が変動しても、出力用トランジスタの
飽和の深さを一定に保つことができ、安定な出力波形を
得ることができる。
Therefore, even if the power supply voltage fluctuates, the saturation depth of the output transistor can be kept constant, and a stable output waveform can be obtained.

[発明の効果] 以上説明した通り、本発明によれば、出力用トランジス
タが“’ ON ”時のベース電流を電源電圧が変動し
ても、一定に保つことにより、電源電”圧の依存性のな
い出力波形を得ることができるものであり□、その工業
的価値は非常に大なるものがある。
[Effects of the Invention] As explained above, according to the present invention, the dependence of the power supply voltage can be reduced by keeping the base current constant when the output transistor is "ON" even if the power supply voltage fluctuates. It is possible to obtain an output waveform free of □, and its industrial value is extremely great.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のECL−TTLレベル゛変換回路の一
実施例を示す回路図、第2図は従来のEcL−TTLレ
ベル変゛換回路の一例を示す回路図である。 01〜Q11:トランジスタ R1−R9:抵抗Io:
定電流源 11 :抵抗R5を流れる電流I :抵抗R
6を流れる電流 I ′:トランジスタQ11の]レクタ電流I :トラ
ンジスタQ5のベース電流 第 1 日 見 2 口
FIG. 1 is a circuit diagram showing an embodiment of the ECL-TTL level conversion circuit of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional ECL-TTL level conversion circuit. 01-Q11: Transistor R1-R9: Resistor Io:
Constant current source 11: Current I flowing through resistor R5: Resistor R
Current I' flowing through transistor Q11: Rector current I of transistor Q1: Base current of transistor Q5

Claims (1)

【特許請求の範囲】[Claims] (1)エミッタを共通とするトランジスタ対からなる電
流切換形論理回路の出力をTTLレベルに変換する回路
において、上記トランジスタ対各々の出力に接続された
エミッタホロワの出力を、コレクタ・エミッタ共通のト
ランジスタ対のベースに各々入力し、該トランジスタ対
の共通エミッタに抵抗、ダイオードを順次接続して定電
流回路を形成し、また、前記エミッタホロワの一方の出
力に接続するトランジスタのエミッタに抵抗を接続し、
該抵抗の他端に出力用トランジスタのベース及び前記定
電流回路によりバイアスされたトランジスタのコレクタ
を接続して構成されたことを特徴とするECL−TTL
レベル変換回路。
(1) In a circuit that converts the output of a current switching type logic circuit consisting of a transistor pair having a common emitter to a TTL level, the output of an emitter follower connected to the output of each of the transistor pairs is converted to a transistor pair having a common collector and emitter. a resistor and a diode are sequentially connected to the common emitter of the transistor pair to form a constant current circuit, and a resistor is connected to the emitter of the transistor connected to one output of the emitter follower,
An ECL-TTL characterized in that the base of an output transistor and the collector of a transistor biased by the constant current circuit are connected to the other end of the resistor.
Level conversion circuit.
JP59143709A 1984-07-11 1984-07-11 Ecl-ttl level converting circuit Pending JPS6123415A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59143709A JPS6123415A (en) 1984-07-11 1984-07-11 Ecl-ttl level converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59143709A JPS6123415A (en) 1984-07-11 1984-07-11 Ecl-ttl level converting circuit

Publications (1)

Publication Number Publication Date
JPS6123415A true JPS6123415A (en) 1986-01-31

Family

ID=15345146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59143709A Pending JPS6123415A (en) 1984-07-11 1984-07-11 Ecl-ttl level converting circuit

Country Status (1)

Country Link
JP (1) JPS6123415A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63163066A (en) * 1987-06-26 1988-07-06 Honda Motor Co Ltd Static oil pressure type continuously variable transmission

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63163066A (en) * 1987-06-26 1988-07-06 Honda Motor Co Ltd Static oil pressure type continuously variable transmission

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