KR950003851Y1 - Low vtg signal transmit switch circuit - Google Patents

Abstract

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Description

Low voltage signaling switch circuit

1 is a circuit diagram of a conventional signal transfer switch.

2 is a circuit diagram of a low voltage signal transfer switch according to the present invention.

* Explanation of symbols for main parts of the drawings

Vcc: Power supply voltage Vi1, VI2: Voltage signal terminal

CLOCK: Clock stage Vout: Voltage signal output stage

Vbias: bias voltage stage Q1 to Q10: transistor

R1 to R4: Resistance l: Current source

GND: Ground ls: Power Current

The present invention relates to a low voltage signal transfer switch circuit, and a low voltage signal transfer switch that is suitable for not affecting the dynamic range, particularly when transmitting a signal to an analog / digital converter requiring low voltage operation. It is about a circuit.

Referring to FIG. 1, a circuit configuration of a conventional signal transfer switch will be described.

The power supply voltage Vcc is applied in parallel and connected in common to the collector terminals of the transistors Q1 and Q3, the current source I, and the transistor Q7 collector terminal after passing through the resistor R2, and the voltage signal terminals Vi1. , Vi2 is connected to the base terminal of the transistors Q3 and Q1, and the emitter terminal of the transistors Q3 and Q1 is connected to the emitter terminal of the transistors Q4 and Q2 and to the collimator terminal of the transistors Q6 and Q5. Connected to the collector terminal and the base terminal of the transistors Q2 and Q4 and the other end of the current source 1 to be connected to the base terminal of the transistor Q7, and to the emitter terminals of the transistors Q5 and Q6 connected. To the collector terminal of transistor Q8, the base terminals of transistors Q5 and Q6 are connected to the positive terminal of the clock terminal CLOCK, respectively, and the bias voltage to the base terminal of transistor Q8. A terminal Vbiss is connected, and the emitter terminal of the transistor Q7 passes the voltage signal output terminal Vout. It is connected to the collector terminal of the transistor Q9, the bias voltage terminal Vbiss is connected to the base terminal of the transistor Q9, and the emitter terminals of the transistors Q8 and Q9 go through the preceding terms R1 and R3 and then ground. (GND) is connected to complete the circuit configuration of the conventional signal transfer switch as a whole.

The emitters of the transistors Q5 and Q6 in the configuration constitute a differential amplifier in common, and the transistors Q8 and Q9 are circuits for generating the power supply current Is, and the transistor Q7 is an output buffer. And transistor Q9 is a current power supply.

Hereinafter, the operation of the circuit configuration will be described.

When the voltage signal terminals Vi1 and Vi2 are separate signal sources, the transistors Q5 and Q6 are alternated according to the phase of the clock signal of the clock terminal CLOCK connected to the base terminal of the transistors Q5 and Q6. When the clock signal of the clock terminal CLOCK is positive, transistor Q5 is "on" and transistor Q6 is "off", and the transistor Q5 is turned on. The transistors Q1 and Q2 are turned on by the " on ", and the transistors Q3 and Q4 are " off " and the transistors Q1 and Q2 are " on " The input signal is transmitted to the emitter terminal of the transistor Q1, is connected to the base terminal of the transistor Q7 through the transistor Q2, and is output to the voltage signal output terminal Vout through the emitter terminal of the transistor Q7.

On the contrary, when the clock signal of the clock terminal CLOCK is negative, transistor Q5 is " off " and transistor Q6 is " on ".

Accordingly, the transistors Q3 and Q4 are "on" so that the input signal of the voltage signal terminal Vi1 is transmitted to the base terminal of the transistor Q3, and continues through the emitter terminal of the transistor Q3 to supply the transistor Q7. The voltage signal is output to the voltage signal output terminal Vout.

However, the conventional signal transfer switch operating as described above is composed of four stages of transistors including the power supply current Is from the power supply voltage Vcc to the ground GND. 0.7 [V] x 4 = 2. When 8 [V] is required, and the real power supply voltage is much higher than the above 2.8 [V] when a basic element such as a resistor enters, the magnitude of the input signal from the voltage signal terminals Vi1 and Vi2 is increased. When large, the problem of dynamic measurement range becomes large, and the analog / digital converter in which the transistor switches at high speed during saturation operation cannot be used.

Therefore, the circuit configuration of the low-voltage signal transfer switch according to the present invention devised to solve the above problems will be described with reference to FIG.

The power supply voltage Vcc is applied to the collector terminal of the transistors Q1, Q2, Q4 and Q5, the current source I, and the collector terminal of the transistor Q7 after passing through the resistor R3 in common and connected in parallel. The voltage signal terminals Vi1 and Vi2 are connected to the base ends of the transistors Q4 and Q1, and the emitter ends of the transistors Q4 and Q1 are connected to the emitter stages of the transistors Q6 and Q3 and the transistors Q9 and Q8. The collector terminals of the transistors Q5 and Q2 are connected and connected, and the collector terminals of the transistors Q1, Q2, Q3, Q4, Q5 and Q6 are connected to each other and connected to the emitter terminals of the transistors Q8 and Q9. And the collector terminal and base terminal of the transistors Q3 and Q6 and the other terminal of the current source I are connected to the base terminal of the transistor Q7, and the emitter terminal of the transistor Q7 is connected to the voltage signal output terminal Vout. Is connected to the collector terminal of transistor Q10, and the bias voltage terminal Vbias is connected to the transistors Q8 and Q9. , Is connected to the base end of Q10, the positive (-) of the clock terminal (CLOCK) is connected to the base end of the transistors (Q2, Q5), respectively, the emitter end of the transistors (Q8, Q9, Q10) Is connected to ground (GND) via (R1, R2, R4) to complete the circuit configuration of the low-voltage signal transfer switch according to the present invention as a whole.

Hereinafter, the operation of the circuit configuration will be described.

First, when the clock signal of the clock terminal CLOCK is (+), since the transistors Q1 and Q2 are differential amplifiers, when the transistor Q2 is "on", the transistor Q1 is "off" and thus the voltage signal terminal ( Since the voltage signal of Vi2 is not input, the transistors Q4 and Q5 are also differential amplifiers, and this time the clock signal of the clock terminal CLOCK is negative, so that the transistor Q5 is "off" and the transistor Q4 is turned off. "On" so that the voltage signal at the voltage signal terminal Vi1 is input through the transistor Q4.

On the other hand, when the clock signal of the clock terminal CLOCK is positively input to the base terminal of the transistor Q2, the voltage of the emitter terminal of the transistor Q2 becomes "high" and the transistor Q3 is also "off". The current source I of the axis flows through the transistor Q6 so that the transistor Q6 is in the " on " state.

Accordingly, the signal Vi1 input through the transistor Q4 is applied to the emitter terminal of the transistor Q4 and the base terminal of the transistor Q7 through the transistor Q6, and the voltage signal through the emitter terminal of the transistor Q7. The voltage signal is output to the output terminal Vout.

In contrast, when the clock signal of the clock terminal CLOCK is negative, the voltage signal of the voltage signal terminal Vi2 passes through the transistor Q1 and through the transistor Q3 and the transistor Q7. The voltage signal is output to (Vout).

Therefore, the voltage signal transfer switch according to the present invention comprises three stages including the current source forming stage coming from the power supply voltage Vcc, so that only the minimum "on" voltage of the transistor is 0.7 [V] x 3 = 2. It becomes 1 [V], and when it is actually operated, it is slightly higher than this. However, since it becomes 0.7 [V] lower than the conventional signal transfer switch circuit, the dynamic measuring range is widened and the signal transfer switching can be sufficiently effected. Will have

Claims (1)

Transistors Q1 and Q2, Q4 and Q5 that receive a (+) (-) clock signal from the clock terminal CLOCK and " on " A transistor Q3 that receives a high " low " output voltage and " off " " on, and " on " off " A bias voltage is applied from a transistor Q6, a transistor Q7 which receives a voltage signal by "on" "off" of the transistors Q1 to Q6, and "on" a bias voltage from a bias voltage terminal Vbias. Low voltage signal transmission comprising a transistor (Q8 to Q10) for making a power supply current (Is) and a voltage signal output terminal (Vout) for receiving and outputting a voltage signal by "on" of the transistor (Q7). Switch circuit.