JPS63318817A - Level converting circuit - Google Patents

Abstract

PURPOSE:To secure the matching between the output voltage of an ECL (emitter coupled logic) circuit and the threshold value of a logic circuit, by converting the difference of potential between the output voltage of a threshold voltage generating circuit and the power supply voltage of the ECL circuit into a current and using this current to change the bias current of the ECL circuit. CONSTITUTION:A level converting circuit which secures the matching of signal levels between an ECL circuit 20 and a logic circuit 30 consists of a threshold voltage generating circuit 40 and a voltage/current converting circuit 50. The circuit 40 produces the voltage equal to the threshold voltage Vt of the circuit 30 based on the negative side voltage V2. Then the circuit 50 converts the potential difference between the output voltage Vt and the power supply voltage Vcc into a current 12. Thus the bias current I1 of a current bias circuit 22 of the circuit 20 is changed by said current I2. In this case, the ratio between both currents I1 and I2 is properly selected together with the values of the load resistances R2 and R3. Thus the matching is secured between the output voltage Vout1 and the threshold voltage Vt of the circuit 30.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to the output voltage level of an emitter-coupled logic circuit;
The present invention relates to a level conversion circuit for matching the threshold voltage level of a logic circuit connected to the output side of the circuit.

(Prior Art) Conventionally, as a technology in this field, there has been a technology as shown in FIG. 2, for example. The configuration will be explained below using figures.

FIG. 2 is a diagram showing a connection state between a conventional emitter-coupled logic circuit and a logic circuit composed of complementary HOS transistors and the like.

Emitter couple logic circuit
d Logic Circuit (hereinafter referred to as EC1 circuit) 1 is load resistance R1, R2 and bipolar type PN
P transistor Ql.

It consists of a differential amplifier circuit 2 consisting of Q2, and a current bias circuit 3 which is connected to this circuit 2 and outputs a constant bias current, and a complementary HO3 transistor (hereinafter referred to as CMO8) is connected to the output side node N1. A logic circuit 10 consisting of the following is connected. Here, Vcc, Vdd
C High 1fJi'R pressure, Vee, Vss C Low power supply voltage, Vinl, Vin2 C Input voltage, Voutl C ECL Output voltage output from DOO12 output side node N1, VOut2 is output side node N2 of logic circuit 10
This is the output voltage output from.

In this circuit, the ECL circuit 1 and the logic circuit 10 are directly connected without providing a level conversion circuit.

Then, when the input voltages Vinl and Vin2 are supplied to the transistors Ql and Q2 of the ELC circuit 1, Vinl>
When Vin2, the transistor Q1 is turned on and the transistor Q2 is turned off, so the output voltage vout 1 on the output side node 141 becomes a high level (hereinafter referred to as H level), which causes the logic circuit 10 to After being inverted, a low level (hereinafter referred to as L level) output voltage VOUT2 is output from the output side node N2. Also,
When Vinl<Vin2, the transistor Q1 is turned off and the transistor 02 is turned on, and the output voltage Vout 1 on the output side node N1 of the ECL circuit 1 becomes L level, which is inverted by the logic circuit 10 and output. Output voltage VOUT2 at H level is output from side node 142.

(Problems to be Solved by the Invention) However, in the circuit with the above configuration, since the ECL circuit 1 and the logic circuit 10 are directly connected without providing a level conversion circuit, the threshold voltage Vt of the logic circuit 10 is Fluctuation,
Alternatively, the power supply voltage Vcc of the ECL circuit 10 and the load resistance R
1. Due to fluctuations in R2, etc., the output voltage V of ECL circuit 1
There is a possibility that the out level and the threshold voltage Vt level of the logic circuit 10 will be in a mismatched state, and as a result, the output voltage VOut2 of the logic circuit 10 will not switch between the H level and the L level, resulting in a decrease in reliability. There was a point.

The present invention solves the problems that the prior art had in the EC.
The present invention provides a level conversion circuit that solves the problem of mismatching between the output voltage level of an L circuit and the threshold voltage level of a logic circuit.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a differential amplifier circuit to which a power supply voltage is applied to the load side, and a current bias circuit connected to this circuit to output a constant bias current. A level conversion circuit for matching an output voltage level of an ECL circuit having a circuit with a threshold voltage level of a logic circuit inputting the output voltage of the emitter-coupled logic circuit; A threshold voltage generation circuit that generates a voltage, and a current/NN pressure change four circuit that converts the potential difference between the output voltage of the threshold voltage generation circuit and the power supply voltage into a current and changes the bias current with the current. It is characterized by

(Function) According to the present invention, since the level conversion circuit is configured as described above, the current/voltage conversion circuit converts the potential difference between the output voltage of the threshold voltage generation circuit and the power supply voltage of the ECL circuit into a current. , the bias current of the ECL circuit is changed by the current. As a result, the high/low binary logic level "Htt" taken by the output voltage of the ECL circuit, the approximately intermediate voltage level in the LPF, and the threshold voltage level of the logic circuit come to match, and the ECL circuit and the logic circuit Signal level consistency can be maintained. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram for explaining a level conversion circuit according to a first embodiment of the present invention.

This level conversion circuit includes an ECL circuit 20 and a logic circuit 30.
This is to match the signal level with the Here, the ECL circuit 20 is composed of a differential amplifier circuit 21 similar to the conventional one, and a current bias circuit 22 that outputs a variable bias current (1). The differential amplifier circuit 21 has two load resistors R1 and R2 to which a high power supply voltage VCC is applied, and each of the load resistors R1 and R2 has a bipolar type NPN.
The collectors of the transistors Ql and 02 are connected in series, and the NPN transistors Ql and
The emitters of Q2 are commonly connected.

Each NPN transistor Ql, Q2 is turned on by an input voltage Vinl, Vin2 supplied to its base, respectively.

It has a function as a switching transistor that turns off, and is configured such that an output voltage Vout i is sent from an output side node connected to the collector of one of the NPN transistors Q2. Also, current bias circuit 2
2 is a bipolar type jIIPN transistor Q3.
The collector of one NPN transistor Q3 is connected to the emitter of NPN transistor Q1, and the collector of one NPN transistor Q3 is connected to the emitter of NPN transistor Q1.
F'N A low power supply voltage Ve is applied to the emitter of transistor Q3.
e is applied. The other NPN i-transistor Q
4 has its base and collector connected to the base of the NPN transistor Q3, and the emitter of the NPN transistor Q4 is commonly connected to the emitter of the NPN transistor Q3. In this current bias circuit 22, when the current 2 flowing between the collector and emitter of the NPN transistor Q4 changes, the NPN transistor
It has a function of changing the current flowing between the collector and emitter of the transistor Q3, that is, the bias current 11 of the differential amplifier circuit 21.

The logic circuit 30 connected to the output side node N1 of the FCL circuit 20 is composed of, for example, a CMOS inverter having a threshold voltage Vt. This C)iOS inverter is
It operates between the positive side voltage v1 and the negative side voltage V2, and inverts the output voltage Vout 1 of the ECL circuit 20 to generate the output voltage V
This is a circuit that sends out2.

A level conversion circuit that performs signal level matching between the ECL circuit 20 and the logic circuit 30 is composed of a threshold voltage generation circuit 40 and a voltage/'current conversion circuit 50.

The threshold voltage generation circuit 40 is a circuit that generates the same voltage as the threshold voltage Vt of the logic circuit 30 using the negative side voltage v2 as a reference. Further, the voltage/current conversion circuit 50 is a circuit that converts the potential difference between the output voltage Vt of the threshold voltage generation circuit 40 and the power supply voltage Vcc into a current ■2, and changes the bias current 11 of the current bias circuit 22 by the current ■2. and
It consists of an operational amplifier AMP, a current setting resistor R3, and a bipolar PNP transistor Q5. The (+) side input terminal of the operational amplifier ARP is connected to the output side of the threshold voltage generation circuit 40, and the (-) side input terminal from which the same voltage as the voltage on the (+) side input terminal is induced is a PNP transistor. Connected to the emitter of Q5. The emitter of PNP transistor Q5 is connected to the high power supply voltage Vcc side via resistor R3, and its PN
The collector of P transistor Q5 is connected to the collector of NPN transistor Q4.

The operation of the circuit configured as above will be explained.

Input voltages Vinl and Vin2 supplied to the gates of transistors Ql and Q2 in the ECL circuit 20 are Vi
When nl>Vin2, the transistor Q1 is turned on and the transistor Q2 is turned off, and an H-level output voltage VOutl is output from the output side node connected to the collector of the transistor 02, which is inverted by the logic circuit 30. An output voltage Vout2 at L level is output. Also V
If inl<Vi+12, transistor 01 is off,
Transistor Q2 is turned on, and output voltage vouti at L level is output from output side node N1, which is inverted by logic circuit 30 and output voltage VOut2 at H level is output.

Here, the same voltage as the threshold voltage Vt of the logic circuit 30 is output from the threshold voltage generation circuit 40, and is supplied to the (+) side input terminal of the operational amplifier ARP in the voltage/' current circuit 50. Then, since the same voltage as the threshold voltage Vt is induced in the emitter of the transistor Q5, the ECL circuit 2
A current I2 that depends on the power supply voltage Vcc of 0, the resistance value of the resistor R3, and the threshold voltage Vt flows into the transistor R4 side of the current bias circuit 22. Note that when the input voltages Vinl and Vin2 of the ECL circuit 20 are the same voltage, that is, E
When the EC1 circuit 20 outputs a voltage that is approximately intermediate between the high and low binary logic levels "Htt" and "1'" that the output voltage Vou of the CL circuit 20 takes, the output voltage Vout i
are the sink current 11 of the current bias circuit 22 and the load resistance R
It is set by the voltage drop due to 2. The current bias circuit 22 sinks the current 11 having a constant ratio to the inflow current I2 from the voltage/current conversion circuit 50 from the differential amplifier circuit 21, so the current bias circuit 22 has load resistances R2 and R3, a power supply voltage VCC, and a threshold voltage. The output voltage vout 1 depending on Vt is E
It will be output from the node N1 of the CL circuit 21.

These relationships can be expressed as follows.

The current 2 flowing into the current bias circuit 22 becomes R3. On the other hand, the input voltages Vinl and V of the ECL circuit 20
When in2 is the same voltage, the currents flowing through the load resistors R1 and R2 are equal, and half of the sink current 1 of the current bias circuit 22 flows through the load resistors R1 and R2, so the output voltage of the ECL circuit 20 Vout
i is Voutl = Vcc −R2−−−・(2)
becomes. Here, if the ratio of the inflow current 2 to the current bias circuit 22 and the sink current 11 is n, the current 11 and I2 are as follows: 11= n - I2 ・(3
). The output voltage vouti of the ECL circuit 20 is calculated from equations (1), (2), and (3). Here, when setting n=2 and R2=R3, for example, equation (4) becomes Voutl==Vt. Therefore, the current ratio n of the current bias circuit 22,
By appropriately selecting the values of the load resistances R2 and R3,
When the input voltages Vinl and Vin2 are the same voltage, the output voltage Vout 1 of the ECl-circuit 20 has the same voltage value as the threshold voltage of the logic circuit 30. Therefore, this embodiment has the following advantages.

The output voltage vout i of the ECL circuit 20 is the threshold voltage Vt of the logic circuit 30 and the power supply voltage V of the ECL circuit 20.
Since the threshold voltage Vt and the power supply voltage Vcc vary depending on CC, the allowable variation range of the threshold voltage Vt and the power supply voltage Vcc can be greatly expanded. Roughly speaking, by using load resistors R1, R2 of the ECL circuit 20 and current setting resistor R3 of the voltage/current conversion circuit 50 that have the same temperature characteristics, the load resistors R1, l?
2, the range of allowable change in resistance value due to temperature can be greatly expanded, thereby making it possible to send out a stable output voltage VOut2 from the logic circuit 30.

FIG. 3 is a circuit diagram for explaining a level conversion circuit according to a second embodiment of the present invention, and the same elements as those in FIG. 1 are given the same reference numerals.

The difference between this circuit and the one in Figure 1 is that the voltage /
'The current conversion circuit 50 is replaced with a voltage/current conversion circuit 50-1 having a different circuit configuration. This voltage/current conversion circuit 50-1 includes a current setting resistor R3 and a PNP transistor Q5 connected in series to the high power supply voltage VCC side.
A bipolar NPN transistor 06 is connected between the high power supply voltage Vcc side of the current setting resistor R3 and the base of the PNP transistor Q5, and further between the emitter of the NPN transistor Q6 and the emitter of the NPN transistor Q4. A constant current source circuit CC8 is connected between them. In the voltage/current conversion circuit 50-1, the voltage drop between the emitter and the base of the PNP transistor Q5 is equal to the voltage drop between the base and emitter of the NPN transistor Q6. By inducing a voltage equal to the output voltage Vt of the supplied threshold voltage generation circuit 40 into the emitter of the PNP transistor Q5, it functions almost the same as the voltage/current conversion circuit 50 of FIG. In this voltage/current conversion circuit 50-1, the output voltage Vt of the threshold voltage generation circuit 40 and the PN
Although a slight potential difference occurs between this and the emitter voltage of the P transistor Q5, it has the advantage that the number of circuit components is reduced.

Note that the present invention is not limited to the illustrated embodiment, and the current bias circuit 22 may be configured with a circuit other than a current mirror circuit, or the logic circuit 30 may be configured with a TTL (transistor-transistor-logic), ECL, etc. other than CMO3. Alternatively, the voltage/current conversion circuit 50.50-1 can be configured with other circuits, or the bipolar transistors shown in Figures 1 and 3 can be configured with unipolar or other semiconductor elements. Various modifications are possible.

(Effects of the Invention) As explained in detail above, since the level conversion circuit is configured of at least a threshold voltage generation circuit and a voltage/'current conversion circuit, the output voltage level of the ECL circuit and the threshold voltage level of the logic circuit are different. Matching is achieved, and a stable logic circuit output can be obtained regardless of fluctuations in the power supply voltage of the ECL circuit or the threshold voltage of the logic circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for explaining a level conversion circuit according to a first embodiment of the present invention, FIG. 2 is an explanatory diagram of a conventional circuit, and FIG. 3 is a level conversion circuit according to a second embodiment of the present invention. FIG. 2 is a circuit diagram for explaining a conversion circuit. 20... ECL circuit, 21... Differential amplifier circuit, 22... Current bias circuit, 30...
...Logic circuit, 40...Threshold voltage generation circuit, 50.50-1...Voltage/' current conversion circuit. Applicant's agent Yasushi Kakimoto! -e4. 1 (Sakura

Claims (1)

[Claims] An output voltage level of an emitter-coupled logic circuit having a differential amplifier circuit to which a power supply voltage is applied to the load side and a current bias circuit connected to this circuit and outputting a constant bias current; A level conversion circuit for matching an output voltage of a combinational logic circuit with a threshold voltage level of an input logic circuit, comprising: a threshold voltage generation circuit that generates the same voltage as the threshold voltage of the logic circuit; 1. A level conversion circuit comprising: a current/voltage conversion circuit that converts a potential difference between an output voltage of the circuit and the power supply voltage into a current, and changes the bias current using the current.