JPS6240814A - Delaying circuit - Google Patents

Abstract

PURPOSE:To adjust a delay time, to make the titled circuit monolithic easily, and to reduce a manufacturing cost by controlling a current value of a current source circuit in a differential amplifying circuit of a diode load. CONSTITUTION:A signal IN of an ECL level to be delayed is inputted to bases of transistors TR 11, 12 of a differential amplifying circuit 10, also a current is supplied an emitter common connecting point from a variable current source circuit 13, and diodes 14, 15 become loads. An output of the circuit 10 is supplied to bases of a pair of differential TRs 21, 22 to which an operating current is supplied from a constant-current source circuit 23, and an output from its load resistance circuit is inputted to a level converting circuit 30. In the circuit 30, an output of a differential amplifying circuit 20 is converted to an ECL level and outputted. In this state, by controlling a current value of the circuit 13, a delay time to the input signal IN can be adjusted.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a delay circuit whose delay time is adjustable.

[Technical background of the invention and its problems] Conventionally, a delay line has been used as a programmable delay circuit that delays a signal for a predetermined time and can freely adjust the delay time according to a control signal. The one used is well known. However, such a delay circuit using a delay@line cannot be made into a monolithic IC and must be realized with individual components, which has the drawback of high manufacturing cost.

[Object of the Invention] This invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide a delay circuit that can be easily made monolithic, thereby realizing a reduction in manufacturing cost. It is in.

[Summary of the Invention] By the way, it is known that in a general differential amplifier circuit, an input signal is delayed and outputted. Furthermore, it is known that the delay time of a differential amplifier circuit can be changed by changing the operating current.

Therefore, in this invention, the emitters of a pair of transistors are commonly connected to form a differential pair, and a signal to be delayed is inputted to the bases of the pair of transistors, and a variable current source circuit is connected to the common emitter. Connect 1, and insert a diode load circuit between each collector and the power supply 2.
The delay time is adjusted by changing the voltage iAt value of the variable current source circuit. Furthermore, by using a diode load circuit, the gain remains unchanged even if the current value of the variable current source circuit changes [7], and changes in the output signal to the next stage are suppressed as much as possible.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a delay circuit according to the present invention. The emitters of the pair of npn transistors LL12 are commonly connected. Both of the above transistors IL
An ECL (emitter-coupled logic) level signal IN to be delayed is inputted to the base of the circuit 12 in a differential format. Furthermore, one end of a variable current source circuit 13 is connected to the common emitter connection point of both transistors IL1.2. -1-2 The other end of the variable current source circuit 13 is connected to the application point of the negative potential -VEE. 1-2 Both transistors 1k +2 diodes 14, +5 in each collector
Each cathode is connected, both diodes 1
The anode of 4.15 is connected to the application point of reference potential GND at JI:. That is, 1-]・Langister I
I, +2 constitute a differential pair, and this differential pair further connects the variable current source circuit 13 to the operating current source and the diode 14.1.
A diode-loaded differential amplifier circuit 1O having 5 as a collector load circuit is constructed.

-4- The collectors of transistors 11 and 12 have npn
The bases of the type transistors 2122 are connected to each other. The emitters of both the first and second transistors 21 and 22 are connected in common, and one end of the constant current source circuit 23 is connected to this emitter common connection point.

-1-2 The other end of the constant current source circuit 23 is at the negative potential -VEE
It is connected to the application point. 1-2 cars l/ransistor 2
One end of each resistor 24.25 is connected to each collector of 1.22, and the other ends of both resistors 24.25 are connected to each other.
- connected to the application point of the reference potential GND.

That is, the transistors 21 and 22 also form a differential pair, and this differential pair is a resistive load differential amplifier circuit in which the constant current source circuit 23 is the operating current source and the resistors 24 and 25 are the collector load circuits. It constitutes 20.

This differential amplifier circuit 20 includes a diode negative 6
The output signal of the differential amplifier circuit 10 of f is supplied as a human input signal.

The bases of npn type transistors 3L 32 are connected to the collectors of the transistors 2L 22, respectively. The collectors of both transistors 31 and 32 are j
(1-) is connected to the application point of the reference potential GND.

Further, one end of each of constant current source circuits 33 and 34 is connected to the emitters of both transistors 3132. The other ends of the constant current source circuits 33 and 34 are both connected to the negative potential -VE.
It is connected to the application point of E.

These transistors 31, 32 and constant current source circuit 33
．． 34 constitutes a level conversion circuit 30 that converts the output level of the resistive load differential amplifier circuit 20 to an ECL (emitter-coupled logic) level, and the level-converted signal is transmitted to each of the two transistors 31 and 32. It is designed to be output from the emitter.

In addition, when this embodiment circuit is integrated into an integrated circuit, an npn type transistor whose collector and base are short-circuited is used as the diode 14 and 15, and the emitter of this transistor is connected to the cathode of the diode, and the collector and base connection point is used. are respectively applied to the anodes of the diodes.

As mentioned above, it is known that in a differential amplifier circuit, an input signal is delayed and outputted, and this delay time is changed by changing the operating current.

Therefore, in this embodiment circuit, a variable current source circuit 13 is provided, and by controlling this current value, the delay time with respect to the human input signal IN is adjusted.

FIG. 2 shows that in the diode-loaded differential amplifier circuit 10, the current value 1y (mA) of the variable current source circuit 13 is 1 (
FIG. 4 is a characteristic diagram showing a change in the delay time Δt (nS) when the value is decreased with reference to the time when the delay time Δt (nS) is Δt (nS). Second
As can be seen in the figure, by decreasing the current value IV from 1 (mA), the delay time Δt increases, and IV becomes 1 (mA).
When the delay time is decreased to 0.25 (...A), which is 1/4 of (mA), the delay time increases by 1.0 (nS) than the reference 11C (.

By the way, in this differential amplifier circuit IO, the diode negative 611
The reason for using is as follows. In other words, when a resistive load is used instead of a diode load, the variable current source circuit 1
If the operating current is changed by changing the current value of 3, the gain of the amplifier circuit changes accordingly, and the output amplitude changes. At this time, there is a risk that the next stage differential amplifier circuit 20 may erroneously judge the level of the human input signal. When a diode is used as a load circuit, the gain of the differential amplifier circuit 10 is determined by the emitter resistance of the transistor 11 or 12.
The ratio between T and the resistance rD of the diode 14 or I5 viewed from the collector of these transistors 11 or 12 is tl. Here, since the diode 14 or 15 is constituted by a transistor whose collector and base are short-circuited, the above-mentioned resistance rD is also the emitter resistance r of the transistor.
It becomes D. Here, since the transistor 1 and the diode 14 and the transistor 2 and the diode 15 have the same operating current, their respective emitter resistances also become equal. Therefore, in this differential amplifier circuit IO, the gain is always kept at 1 even if the energization value of the variable current source circuit 13 is changed. Therefore, if the amplitude of the input signal IN is constant, the output amplitude of the differential amplifier circuit IO will also be constant.

The constant amplitude signal delayed by an arbitrary amount of time in the differential amplifier circuit 10 is then amplified with sufficient gain in the differential amplifier circuit 20 with a resistive load, so that the small amplitude can be transmitted to the next stage. and is supplied to the level conversion circuit 30. This level conversion circuit 30 converts the level of the output signal of the -1- differential amplifier circuit 20 so that, for example, the "H" level is approximately -0.85V, and the "L" level is approximately -1.60V.
It outputs a signal at an ECL level of about V.

In this way, the circuit of the above embodiment is composed of NPN (npn) transistors, resistors, diodes, etc. that can be formed in a normal bipolar integrated circuit, so it can be easily integrated into a monolithic integrated circuit.
It is possible to reduce the manufacturing cost.

In addition, in the above example circuit, the input and output are each ECL.
Since the circuits are level compatible, the necessary delay time can be obtained by preparing a plurality of circuits of this embodiment and connecting them in multiple stages.

1] Variable current source circuit 13 used in the example circuit
Various types of well-known forms can be used as
For example, the one shown in FIG. 3 can be used. This variable current source circuit is connected to the inverting input terminal (-) of the operational amplifier circuit 41.
Connect the reference voltage V ref' to the non-inverting input terminal (+
) includes one constant current source 42 and a plurality of switches 43.
A feedback resistor R is inserted between the output terminal and the non-inverting input terminal of the operational amplifier circuit 41, and an npn type transistor is connected to the output terminal of the operational amplifier circuit 41. 45 is connected to the emitter of this transistor 45 and a negative potential power supply voltage -VEE.
A resistor RE is inserted between the two. The collector of the transistor 45 is connected to the transistor 11.
, 12 common emitters.

In this circuit, by increasing the number of switches 43 that are closed, the current flowing through the resistor R increases, and the voltage drop (1) across this resistor R increases.

Here, the emitter potential of the transistor 45 is VBE, where the voltage between the base and emitter of the transistor 45 is VBE.
ref'+V1+VBE, the current flowing through the resistor RE, that is, the value of the output current IV as a current source circuit is given by the following equation.

ly −(Vref +V 1−VB E ) /R
E...1 Therefore, by changing the current flowing through the resistor R in this circuit and changing the value of the voltage drop generated across the resistor R, the output current value as a current source circuit can be adjusted.

(Effects of the Invention) As explained below, according to the present invention, the emitters of a pair of transistors are commonly connected to form a differential pair, and a signal to be delayed is input to the bases of the pair of transistors. , a variable current source circuit is connected to the common emitter, and a diode load circuit is inserted between each collector and the power supply, and the delay time is adjusted by changing the current value of the above-mentioned ii7 variable current source circuit. Therefore, it is possible to provide a delay circuit that can be easily made monolithic, thereby reducing the manufacturing cost.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the delay circuit according to the present invention, FIG. 2 is a characteristic diagram of the embodiment circuit described in -1-, and FIG.
The figure is a circuit diagram specifically showing a part of the circuit of the embodiment described in 1-. 10, 20... Differential amplifier circuit, II, 12.21.
22.31°32...npn type transistor, 13
...variable current source circuit, 14.15...diode,
23.33.34...constant current source circuit, 24.25...
・Resistance, 30...Level conversion circuit. Applicant's agent Patent attorney Takehiko Suzue-11=

Claims (2)

[Claims] (1) A differential pair consisting of a pair of transistors in which a signal to be delayed is input to the base and whose emitters are commonly connected; a variable current source circuit connected to the common emitters of the pair of transistors; A delay circuit comprising a diode load circuit inserted between each collector of the transistor and a power supply. (2) The delay circuit according to claim 1, wherein the diode load circuit is each constituted by a transistor whose collector and base are short-circuited.