JP3470835B2 - Operational amplifier - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed operational amplifier, and more particularly to an operational amplifier with improved input / output characteristics. 2. Description of the Related Art FIG. 2 is a circuit diagram of a conventional operational amplifier which operates at high speed with low current consumption. In FIG. 2, 1 is an inverting input terminal, and 2 is a non-inverting input terminal. Q1 and Q2 have their emitters connected in common to the first current source 3 (current I) and
, N5, Q5,
Q6 is a PNP transistor whose emitter is commonly connected to a second current source 5 (current I) to form a second differential circuit 6, wherein the bases of the transistors Q1 and Q5 are commonly connected to the inverting input terminal 1. And the transistors Q2 and Q
The base 6 is commonly connected to the non-inverting input terminal 2.
Diode D1 is the load of transistor Q1, and diode D2 is the load of transistor Q5. The output of the first differential circuit 4 is a transistor Q
PNP transistors Q9-Q connected to
The output of the second differential circuit 6 is taken out by a Wilson-type first current mirror circuit 7 comprising an NPN transistor 11 and a Wilson-type second current comprising NPN transistors Q12 to Q14 connected to the collector of a transistor Q6. It is taken out by the mirror circuit 8. The above-mentioned transistors Q1, Q2, Q5, Q6, Q9 to Q14, constant current sources 3, 5 and diodes D1, D2 constitute a double (complementary) differential input stage 9. A PNP transistor Q21 and an NPN transistor Q22 operate in reverse according to the difference between the output currents of the first and second current mirror circuits 7 and 8, and a PNP transistor Q20 operates in the first current mirror circuit 7. NPN transistor Q17 operates in proportion to the output current of second current mirror circuit 8. The above transistors Q17 and Q2
The output bias stage 10 is constituted by 0 to Q22. The NPN transistor Q23 is an output transistor operated by a difference between the collector current of the transistor Q20 and the emitter current of the transistor Q21, and the PNP transistor Q24 is an output transistor operated by a difference between the collector current of the transistor Q17 and the emitter current of the transistor Q22. The emitters are connected to the output terminal 12 via bias setting resistors R2 and R3, respectively, to form emitter followers. Capacitor C2 and resistor R
1 constitutes a feedback circuit for phase compensation. The above transistors Q23 and Q24, resistors R1 to R3, and capacitor C1
Thus, a class B push-pull output stage 11 is configured. 1
3 is a high-potential power supply terminal, and 14 is a low-potential power supply terminal. In output stage 11, transistor Q23
The base-emitter voltage V _BEQ23 of the transistor Q
Is canceled by the base-emitter voltage V _BEQ21 of 21, the base-emitter voltage V _BEQ24 of the transistor Q24 is canceled by the base-emitter voltage V _BEQ22 transistor Q22, crossover distortion is prevented thereby. Next, the operation will be described. In the operational amplifier shown in FIG. 2, when the input voltage of input terminal 1 is higher than the input voltage of input terminal 2, the collector current of transistor Q2 decreases and the collector current of transistor Q6 increases, so that the first current mirror The output current of the circuit 7 decreases, the output current of the second current mirror circuit 8 increases, and the voltage at the point A decreases. As a result, the output impedance of transistor Q20 increases and that of transistor Q21 decreases, so that the base potential of output transistor Q23 decreases and its emitter current decreases. Further, since the output impedance of the transistor Q17 decreases and the output impedance of the transistor Q22 increases, the base potential of the output transistor Q24 decreases,
Its emitter current increases. Therefore, a current is drawn from the output terminal 12, and the output voltage drops. When the input voltage of the input terminal 1 is lower than the input voltage of the input terminal 2, the operation is the reverse of the above, and a current is discharged from the output terminal 12, and the output voltage increases. [0010] By the way, the power supply terminal 1
When the potential difference between the terminals 3 and 14 is about 3 V and the input voltage is higher than the voltage of the input terminal 100 by 100 mV or more, the collector current of the transistor Q 6 is reduced by the current of the constant current source 5. I, and the collector current of the transistor Q2 becomes zero. Therefore, the collector currents of the transistors Q13 and Q14 of the second current mirror circuit 8 should also be I, but since the output current of the first current mirror circuit 7 is 0, the transistors Q14 and Q14
No collector current flows through Q13. Therefore, the transistor Q14 is saturated,
The collector voltage becomes lower than the base voltage, so that the currents of the transistors Q14 and Q13, which should be determined by the collector current of the transistor Q12, do not flow, and the current mirror operation condition is broken. Therefore, transistor Q17
Of the output transistor Q24
Also have high impedance. Also, the transistor Q23
At this time has a high impedance due to normal operation. Therefore, the voltage appearing at the output terminal 12 is the midpoint voltage.
Therefore, there arises a problem that monotonicity (linearity) between the input voltage applied to the input terminals 1 and 2 and the output voltage obtained at the output terminal 12 cannot be maintained. This becomes remarkable under heavy load. Further, when this circuit is made into an IC,
When the transistor Q14 saturates, a parasitic PNP transistor Q14 'is formed by the base, collector and substrate (SUB) of the transistor Q14, and this bypasses the collector current of the transistor Q6. There is also a problem that the base current supply path of the element is lost, the current mirror operation stops, and the output current becomes zero. The present invention has been made in view of the above points, and has as its object to operate normally even at a large input, to ensure monotonicity, and to stabilize circuit functions. It is an object of the present invention to provide an operational amplifier. [0014] A first differential circuit comprising a base and two transistors individually connected to first and second input terminals and a first current source, A second differential circuit having a base individually connected to the first and second input terminals and including two transistors having opposite polarities to the transistor and a second current source; A first Wilson-type current mirror circuit using a collector current of a transistor whose base is connected to the second input terminal of the driving circuit as a reference current; and a second input of the second differential circuit. A second Wilson-type current mirror circuit using a collector current of the transistor whose base is connected to the terminal as a reference current, and a second current mirror circuit of the first differential circuit;
A transistor whose base is connected to the first input terminal
Current mirror using the collector current of the reference as a reference current
Circuit and a first input terminal of the second differential circuit.
The collector current of the transistor to which the source is connected.
A fourth current mirror circuit of quasi current, the first output current of the current mirror circuit and the current and the third corresponding to the difference between the output current of said second current mirror circuit
According to the difference current from the output current of the current mirror circuit
A first output transistor having an emitter connected to an output terminal and an output of the first current mirror circuit.
Difference between the current and the output current of the second current mirror circuit
And the output of the fourth current mirror circuit.
Comprising a second output transistor having an emitter is driven according to the difference of the current of the power current is connected to the output terminal, the
And the first and second output transistors are of class B
It was configured to work as a sprue output stage . According to the present invention, the current corresponding to the output current of the third current mirror circuit and the current corresponding to the output current of the fourth current mirror circuit are accurately supplied to the output bias stage according to the input voltage. Supplied. Therefore, compared with the case where the output currents of the first and second current mirror circuits are used as they are, the operation of the first and second current mirror circuits is not affected. Therefore, even when the operating conditions of the first and second current mirror circuits are broken at the time of a large input, the monotonicity of the input / output characteristics is accurately maintained. Embodiments of the present invention will be described below. FIG. 1 is a circuit diagram of an operational amplifier according to one embodiment. The same components as those of the operational amplifier shown in FIG. 2 are denoted by the same reference numerals. In this embodiment, in the double differential input stage 9, in addition to the circuit shown in FIG. 2, the diode-connected PN for load is connected to the collector of the transistor Q1 of the first differential circuit 4.
A P transistor Q3 and a PNP transistor Q4 are connected in series, and the transistor Q4 and the PNP transistor Q
15 constitute a third current mirror circuit 15. Further, a diode-connected NPN transistor Q7 and a transistor Q8 for load use are connected in series to the collector of the transistor Q5 of the second differential circuit 6, and the transistor Q8 and the NPN transistor Q18 connect the fourth current mirror circuit 16 Is configured. The above-mentioned transistor Q15 is connected in series with an NPN transistor Q16, and its transistor Q1
6 and the transistor Q17 of the output bias stage 10
Of the current mirror circuit 17 of FIG. The transistor Q18 is connected in series with a PNP transistor Q19, and the transistor Q19 and the transistor Q20 of the output bias stage 10 constitute a sixth current mirror circuit 18. C1 is a feedback capacitor for phase compensation. In this embodiment, when a voltage higher than that of the input terminal 2 is input to the input terminal 1, the transistor Q
2, the collector current of the transistor Q6 increases. Therefore, the output current of the first current mirror circuit 7 decreases and the output current of the second current mirror circuit 8 increases, so that the potential at the point A decreases. Therefore, the bias of the transistor Q21 becomes deep, and the bias of the transistor Q22 becomes shallow. On the other hand, the output current of the third current mirror circuit 15 increases, and the output current of the fifth current mirror circuit 17 receiving the output current also increases. Further, the output current of the fourth current mirror circuit 16 decreases, and the output current of the sixth current mirror circuit 18 receiving the output current also decreases. As a result, the output impedance of the transistor Q20 increases, and the output impedance of the transistor 21 decreases.
Bias becomes shallower. Further, since the output impedance of the transistor Q17 decreases and the output impedance of the transistor 22 increases, the bias of the output transistor Q24 increases. Thus, the output terminal 12
, The current is drawn, and the output voltage drops. Conversely, when a voltage lower than the input terminal 2 is input to the input terminal 1, the transistors Q2, Q5
Increases, the collector currents of transistors Q1 and Q6 decrease, and the operation opposite to the above is performed, and the output voltage increases. Here, when the potential difference between the power supply terminals 13 and 14 is about 3 V, at the time of a large input where the voltage of the input terminal 1 becomes higher than the voltage of the input terminal 2 by 100 mV or more, as described above. The collector current of the transistor Q6 becomes the current I of the constant current source 5 , the collector current of the transistor Q2 becomes 0, the potential at the point A decreases, and the transistor Q14 saturates. Therefore, the transistor Q21 has a small output impedance (almost minimum), and the transistor Q22 has a large output impedance (almost maximum).
I do. At this time, the output current of the third current mirror circuit 15 increases (substantially maximizes) and the output current of the fourth current mirror circuit 16 decreases (substantially minimizes). The current of the circuit 17 increases, the output impedance of the transistor Q17 decreases (substantially minimum), the current of the sixth current mirror circuit 18 decreases, and the output impedance of the transistor Q20 increases (substantially maximum). As described above, the emitter current of the output transistor Q23 decreases (substantially minimizes), and the output transistor Q2
In No. 4, the emitter current increases (substantially maximizes), the output voltage decreases to approximately the minimum value, and normal operation is ensured. Contrary to the above, at the time of a large input of the opposite polarity such that the voltage of the input terminal 1 becomes lower than the voltage of the input terminal 2 by 100 mV or more, the voltage at the point A becomes high (substantially maximum) and the transistor Q21 Has a high (substantially maximum) output impedance and the output impedance of the transistor Q22 has a low (almost minimum) output impedance. Also, the transistor Q1
7, the output impedance of the transistor Q20 becomes high (almost maximum), the output impedance of the transistor Q20 becomes low (almost minimum), the emitter current of the output transistor Q23 increases (almost maximum), and the emitter current of the output transistor Q24 decreases ( (Substantially the lowest), the output voltage increases to almost the maximum value, and normal operation is ensured. As described above, in this embodiment, the third and fifth current mirror circuits for controlling the transistor Q17 are different from the first and second current mirror circuits 7 and 8 for controlling the transistors Q21 and Q22. 15 and 17, and the fourth and sixth current mirror circuits 16 and 18 for controlling the transistor Q20 are separated from each other.
17, Q20 are the first and second current mirror circuits 7, 8
, The monotonicity between the input and output signals can be maintained even if the current mirror operation of the first and second current mirror circuits 7 and 8 breaks down when a large signal is input. Become like The transistors to be added are PNP transistors Q4, Q15, Q19, NP
The N transistors Q8, Q18 and Q16 have a small increase in the number of elements and a small increase in current consumption. As described above, according to the present invention, the output bias stage is controlled by the third and fourth current mirror circuits separated from the first and second current mirror circuits.
Even at the time of large input, regardless of the current mirror operation of the first and second current mirror circuits, the output bias stage operates normally, and the monotonicity of the input / output characteristics can be secured. Also, the current consumption is only slightly increased.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of an operational amplifier according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a conventional operational amplifier. [Description of Signs] 1: First input terminal, 2: Second input terminal, 3: First constant current source, 4: First differential circuit, 5: Second constant current source,
6: a second differential circuit, 7: a first current mirror circuit,
8: second current mirror circuit, 9: double differential input stage,
10: output bias stage, 11: output stage, 12: output terminal, 13: high potential power terminal, 14: low potential power terminal, 1
5: third current mirror circuit, 16: fourth current mirror circuit, 17: fifth current mirror circuit, 18:
Sixth current mirror circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03F 3/45 H03F 3/30 H03F 3/34

Claims (1)

(57) Claims: 1. A first differential circuit having a base composed of two transistors and a first current source respectively connected to first and second input terminals. A second differential circuit whose base is individually connected to the first and second input terminals and is composed of two transistors having a polarity opposite to that of the transistor and a second current source; A first Wilson-type current mirror circuit using a collector current of a transistor whose base is connected to the second input terminal of the second differential circuit as a reference current; and a second current mirror circuit of the second differential circuit. A second current mirror circuit of a Wilson type using the collector current of the transistor whose base is connected to the input terminal of the second differential mirror as a reference current, and a base connected to the first input terminal of the first differential circuit.
The collector current of the connected transistor is
A base is connected to the third current mirror circuit to be connected and the first input terminal of the second differential circuit.
The collector current of the connected transistor is
And a current corresponding to a difference between the output current of the first current mirror circuit and the output current of the second current mirror circuit.
And the difference between the output current of the third current mirror circuit and
A first output transistor driven according to a current and having an emitter connected to the output terminal; an output current of the first current mirror circuit and a second output transistor;
Current corresponding to the difference from the output current of the current mirror circuit
And the difference between the output current of the fourth current mirror circuit and
Comprising a second output transistor having an emitter being driven is connected to the output terminal in accordance with the current, the said first and second output transistors are Class B push
An operational amplifier characterized by acting as a pull output stage .