JPH0525331B2 - - Google Patents

Info

Publication number
JPH0525331B2
JPH0525331B2 JP61314972A JP31497286A JPH0525331B2 JP H0525331 B2 JPH0525331 B2 JP H0525331B2 JP 61314972 A JP61314972 A JP 61314972A JP 31497286 A JP31497286 A JP 31497286A JP H0525331 B2 JPH0525331 B2 JP H0525331B2
Authority
JP
Japan
Prior art keywords
signal
address strobe
strobe signal
column address
row address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61314972A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63163938A (ja
Inventor
Takeyuki Sudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP31497286A priority Critical patent/JPS63163938A/ja
Publication of JPS63163938A publication Critical patent/JPS63163938A/ja
Publication of JPH0525331B2 publication Critical patent/JPH0525331B2/ja
Granted legal-status Critical Current

Links

JP31497286A 1986-12-26 1986-12-26 ダイナミツクramコントロ−ラ Granted JPS63163938A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31497286A JPS63163938A (ja) 1986-12-26 1986-12-26 ダイナミツクramコントロ−ラ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31497286A JPS63163938A (ja) 1986-12-26 1986-12-26 ダイナミツクramコントロ−ラ

Publications (2)

Publication Number Publication Date
JPS63163938A JPS63163938A (ja) 1988-07-07
JPH0525331B2 true JPH0525331B2 (enrdf_load_html_response) 1993-04-12

Family

ID=18059882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31497286A Granted JPS63163938A (ja) 1986-12-26 1986-12-26 ダイナミツクramコントロ−ラ

Country Status (1)

Country Link
JP (1) JPS63163938A (enrdf_load_html_response)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2118662C (en) * 1993-03-22 1999-07-13 Paul A. Santeler Memory controller having all dram address and control signals provided synchronously from a single device
JP2624155B2 (ja) * 1993-12-20 1997-06-25 日本電気株式会社 表示用メモリ書き込みデータ制御回路
JPH07234824A (ja) * 1994-02-24 1995-09-05 Nec Corp 記憶制御装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5426328U (enrdf_load_html_response) * 1977-07-22 1979-02-21
JPS5968068A (ja) * 1982-10-12 1984-04-17 Nec Corp メモリボ−ド
JPS6074174A (ja) * 1983-09-29 1985-04-26 Fujitsu Ltd メモリ・アクセス方式

Also Published As

Publication number Publication date
JPS63163938A (ja) 1988-07-07

Similar Documents

Publication Publication Date Title
JP3590413B2 (ja) メモリ制御装置
US20020144049A1 (en) Multiple mode memory module
JPH03254497A (ja) マイクロコンピュータ
JP2005322265A (ja) 処理システム
EP0307945B1 (en) Memory control apparatus for use in a data processing system
US5640517A (en) Method and apparatus for masters to command a slave whether to transfer data in a sequential or non-sequential burst order
US7707328B2 (en) Memory access control circuit
US5530955A (en) Page memory device capable of short cycle access of different pages by a plurality of data processors
US5901298A (en) Method for utilizing a single multiplex address bus between DRAM, SRAM and ROM
US4964037A (en) Memory addressing arrangement
JPH0525331B2 (enrdf_load_html_response)
JP2827361B2 (ja) 半導体メモリ装置
US6041015A (en) Semiconductor type memory device having consecutive access to arbitrary memory address
JP3253668B2 (ja) メモリ装置とこれを用いたデータ処理システム
JPS61227295A (ja) 半導体記憶装置
JPH0528760A (ja) 半導体メモリ
JPH0525330B2 (enrdf_load_html_response)
JP3314395B2 (ja) メモリ制御装置
JP3318125B2 (ja) Dram制御回路
JPH0561769A (ja) メモリ・アクセス方法
JP3389152B2 (ja) Dram制御回路
JP2570271B2 (ja) 半導体メモリ制御装置
JPH05101650A (ja) ダイナミツクメモリのリフレツシユ方式
KR890008560Y1 (ko) Dram 타이밍 발생기
JPH0554646A (ja) メモリ装置及びそのダイナミツクramリフレツシユ方式

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees