JPH0524541B2 - - Google Patents

Info

Publication number
JPH0524541B2
JPH0524541B2 JP61256070A JP25607086A JPH0524541B2 JP H0524541 B2 JPH0524541 B2 JP H0524541B2 JP 61256070 A JP61256070 A JP 61256070A JP 25607086 A JP25607086 A JP 25607086A JP H0524541 B2 JPH0524541 B2 JP H0524541B2
Authority
JP
Japan
Prior art keywords
data
command
channel
adapter
shared memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61256070A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63109560A (ja
Inventor
Hiromi Sugawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP25607086A priority Critical patent/JPS63109560A/ja
Publication of JPS63109560A publication Critical patent/JPS63109560A/ja
Publication of JPH0524541B2 publication Critical patent/JPH0524541B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP25607086A 1986-10-28 1986-10-28 ファイル制御装置におけるコマンド制御方法 Granted JPS63109560A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25607086A JPS63109560A (ja) 1986-10-28 1986-10-28 ファイル制御装置におけるコマンド制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25607086A JPS63109560A (ja) 1986-10-28 1986-10-28 ファイル制御装置におけるコマンド制御方法

Publications (2)

Publication Number Publication Date
JPS63109560A JPS63109560A (ja) 1988-05-14
JPH0524541B2 true JPH0524541B2 (enrdf_load_stackoverflow) 1993-04-08

Family

ID=17287479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25607086A Granted JPS63109560A (ja) 1986-10-28 1986-10-28 ファイル制御装置におけるコマンド制御方法

Country Status (1)

Country Link
JP (1) JPS63109560A (enrdf_load_stackoverflow)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148445A (en) * 1978-05-15 1979-11-20 Nec Corp Data transfer control unit

Also Published As

Publication number Publication date
JPS63109560A (ja) 1988-05-14

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