JPH0523452B2 - - Google Patents

Info

Publication number
JPH0523452B2
JPH0523452B2 JP61030314A JP3031486A JPH0523452B2 JP H0523452 B2 JPH0523452 B2 JP H0523452B2 JP 61030314 A JP61030314 A JP 61030314A JP 3031486 A JP3031486 A JP 3031486A JP H0523452 B2 JPH0523452 B2 JP H0523452B2
Authority
JP
Japan
Prior art keywords
bus
circuit
output
line driver
masters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61030314A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62187954A (ja
Inventor
Makoto Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3031486A priority Critical patent/JPS62187954A/ja
Publication of JPS62187954A publication Critical patent/JPS62187954A/ja
Publication of JPH0523452B2 publication Critical patent/JPH0523452B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP3031486A 1986-02-14 1986-02-14 バス制御回路 Granted JPS62187954A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3031486A JPS62187954A (ja) 1986-02-14 1986-02-14 バス制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3031486A JPS62187954A (ja) 1986-02-14 1986-02-14 バス制御回路

Publications (2)

Publication Number Publication Date
JPS62187954A JPS62187954A (ja) 1987-08-17
JPH0523452B2 true JPH0523452B2 (enrdf_load_stackoverflow) 1993-04-02

Family

ID=12300329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3031486A Granted JPS62187954A (ja) 1986-02-14 1986-02-14 バス制御回路

Country Status (1)

Country Link
JP (1) JPS62187954A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831003B2 (ja) * 1989-10-04 1996-03-27 日本電気株式会社 バス占有回路
JP3566630B2 (ja) 2000-07-28 2004-09-15 Ｎｅｃマイクロシステム株式会社 カードシステム、それに用いるｉｃカード及びカードリーダライタ

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1093493B (it) * 1978-03-23 1985-07-19 Honeywell Inf Systems Circuito di trasmissione bidirezionale di segnali interbloccati

Also Published As

Publication number Publication date
JPS62187954A (ja) 1987-08-17

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees