JPH05226398A - 集積回路モジュール - Google Patents

集積回路モジュール

Info

Publication number
JPH05226398A
JPH05226398A JP4029782A JP2978292A JPH05226398A JP H05226398 A JPH05226398 A JP H05226398A JP 4029782 A JP4029782 A JP 4029782A JP 2978292 A JP2978292 A JP 2978292A JP H05226398 A JPH05226398 A JP H05226398A
Authority
JP
Japan
Prior art keywords
integrated circuit
wiring
circuit module
substrate
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4029782A
Other languages
English (en)
Inventor
Norio Nitta
法生 新田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP4029782A priority Critical patent/JPH05226398A/ja
Publication of JPH05226398A publication Critical patent/JPH05226398A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 （修正有） 【目的】 高密度実装可能な配線自由度の高い絶縁被覆
ワイヤを用いた集積回路モジュールを提供する。 【構成】 集積回路素子を基板に載せ、素子の外部電極
パッド１１ａ，１１ｂと基板上に構成された共通電極パ
ッド１９を絶縁被覆ワイヤ１８で接続する。 【効果】 高密度配線においても本発明によれば自由に
配線でき、画期的高密度混成集積回路モジュールを実現
することができる。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は集積回路上で高密度配置
される回路素子間に配線された集積回路モジュールに関
するものである。
【０００２】
【従来の技術】従来、例えば複数個素子を実装した混成
集積回路においては樹脂封止等パッケージングされたＩ
Ｃを基板上で配線し構成していた。ところがＩＣをチッ
プのまま配置し、ボンディングワイヤで直接基板に実装
すればパッケージの面積部分は省略でき、高密度実装が
可能となる。
【０００３】しかし、近年のＩＣの高集積化によって外
部電極パッドの数が増し、狭ピッチ化したためそのよう
な配線を施した場合互いに接触し、電気的に短絡してし
まう危険性がある。また、集積回路実装ではワイヤ線の
交互配線を皆無にしなければならないため、これが各素
子の配置、配置密度に大きな制約を与え、又仕様変更に
より電極配置が変更された場合でも回路パタンの変更を
余儀なくされ、多大の時間、労力、費用を要するという
欠点がある。
【０００４】
【発明が解決しようとする課題】本発明は、上記した従
来の欠点を除去し、多ピン化・高密度化実装に対応した
絶縁被覆ワイヤを任意配線に積極的に使用するためにな
されたもので、従来、ワイヤボンディングに用いられて
きた通常のボンディング装置をそのまま使い、絶縁被覆
ワイヤ用にボンディング装置のもつパラメータと装置の
一部に若干の修正を加えたボンディング法を用いた任意
の集積回路外部電極端子パッド間または任意の外部電極
端子パッド、配線基板上または集積回路上の共通電極端
子パッド間の配線方式に関し、絶縁被覆ワイヤを使った
配線実装法を用いた集積回路モジュールを提供すること
を目的とする。
【０００５】
【課題を解決するための手段】本発明の要旨とするとこ
ろは、集積回路素子の外部接続パッド部と他の集積回路
外部接続パッド部または回路配線基板上の共通パッドと
の間を絶縁被覆ワイヤを用いて配線してあり、電気的に
分岐させる共通パッドを基板上または集積回路素子上に
もつことを特徴とする集積回路モジュールにある。
【０００６】
【作用・効果】本発明の実施には、通常のボンディング
装置を特別な改造をせずに、接触しても十分な絶縁耐力
をもち、裸金ワイヤと同程度の接合性をもつ絶縁被覆ワ
イヤを集積回路間、および集積回路と配線基板の間の接
合に使用する。接触による短絡の危険性のない配線は、
配線しようとする電極がワイヤの交差するような配置に
あっても何の配慮もなく配線することが可能となる。
【０００７】以上の如く、自由な配線を実現する本発明
に従った配線方式は画期的な混成集積回路モジュール実
現に寄与するものである。
【０００８】
【実施例】以下本発明を実施例に従って説明する。 実施例１ メモリーカードにおいて、共通パッドを基板上に設けて
ベアチップパッドと共通パッドを絶縁被覆ワイヤを使用
して接続した。ＴＳＯＰパッケージ実装された４Ｍｂｉ
ｔＤＲＡＭ８個使用の８ＭＢのメモリーカードは、既存
の実装では基板両面を使っていたが、本発明では同じ４
ＭｂｉｔＤＲＡＭメモリーベアチップが片面に実装され
ただけで済み、およそ２倍の実装集積密度が得られたこ
とになり、同じ体積ならば２倍の記憶容量が実現した。
【０００９】実施例２ 複数ＡＳＩＣ等ロジックＩＣの電極パッド間を配線し
た。ベアチップ間距離（チップの寸法を含む）が半分に
なり、実装面積も４分の１が実現する。配線がほぼ半分
になったことにより線間容量が減少し、遅延等の問題が
解決され、高速動作可能なＩＣモジュールが実現した。
【００１０】
【発明の効果】以上説明したように、本発明によれば絶
縁被覆されたワイヤにより任意自由配線された実装法で
は、接触による電気的短絡による制約から開放され、集
積回路電極端子パッドから他のパッドへの直接配線や、
基板上や集積回路上に共通電極パッドを設けることによ
って、さらに外部への接続自由度をもった集積回路モジ
ュールを提供することができる。
【図面の簡単な説明】
【図１】素子間を通常ワイヤを使った交差接続の概略図
である。
【図２】本発明による共通パッドを持った交差接続の概
略図である。
【図３】本発明による直接的な交差接続の概略図であ
る。
【符号の説明】
１１ａ, １１ｂ ＩＣチップ外部端子パッド １４ 基板 １５ 基板上電線 １６ 基板上電極パッド １７ 貫通電極 １８ 絶縁被覆ワイヤ １９ 共通電極パッド

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】 集積回路素子の外部接続パッド部と他の
    集積回路外部接続パッド部または回路配線基板上の共通
    パッドとの間を絶縁被覆ワイヤを用いて配線してあり、
    電気的に分岐させる共通パッドを基板上または集積回路
    素子上にもつことを特徴とする集積回路モジュール。
JP4029782A 1992-02-17 1992-02-17 集積回路モジュール Withdrawn JPH05226398A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4029782A JPH05226398A (ja) 1992-02-17 1992-02-17 集積回路モジュール

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4029782A JPH05226398A (ja) 1992-02-17 1992-02-17 集積回路モジュール

Publications (1)

Publication Number Publication Date
JPH05226398A true JPH05226398A (ja) 1993-09-03

Family

ID=12285587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4029782A Withdrawn JPH05226398A (ja) 1992-02-17 1992-02-17 集積回路モジュール

Country Status (1)

Country Link
JP (1) JPH05226398A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998026452A1 (en) * 1996-12-09 1998-06-18 Microbonds, Inc. High density integrated circuits and the method of packaging the same
CN100461398C (zh) * 2004-02-26 2009-02-11 飞思卡尔半导体公司 具有交叉导体装配件的半导体封装件及制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998026452A1 (en) * 1996-12-09 1998-06-18 Microbonds, Inc. High density integrated circuits and the method of packaging the same
CN100461398C (zh) * 2004-02-26 2009-02-11 飞思卡尔半导体公司 具有交叉导体装配件的半导体封装件及制造方法

Similar Documents

Publication Publication Date Title
US6667560B2 (en) Board on chip ball grid array
US4956694A (en) Integrated circuit chip stacking
US5451815A (en) Semiconductor device with surface mount package adapted for vertical mounting
US6150729A (en) Routing density enhancement for semiconductor BGA packages and printed wiring boards
US5789816A (en) Multiple-chip integrated circuit package including a dummy chip
JP3059097B2 (ja) 電子回路盤とその製造方法
US5399904A (en) Array type semiconductor device having insulating circuit board
US20240186293A1 (en) Semiconductor package having chip stack
JP2001156251A (ja) 半導体装置
JPH04273451A (ja) 半導体装置
EP0166401A2 (en) Circuit module
CN112885808B (zh) 封装基板以及封装结构
US5982654A (en) System for connecting semiconductor devices
US5451812A (en) Leadframe for semiconductor devices
US8258616B1 (en) Semiconductor dice having a shielded area created under bond wires connecting pairs of bonding pads
JP2638758B2 (ja) 積層型の半導体パッケージ及び積層型のパッケージソケット
JPH05226398A (ja) 集積回路モジュール
CN213692038U (zh) 一种多基岛的sop封装引线框架
TWM565880U (zh) Universal adapter circuit layer for semiconductor package structure
JPS5854646A (ja) 混成集積回路装置
JPS62104149A (ja) 集積回路チツプ・モジユ−ル
JPS63182845A (ja) 半導体装置
JP2004031432A (ja) 半導体装置
KR100235495B1 (ko) 반도체 장치
KR950003908B1 (ko) 반도체 리드 프레임

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990518