JPH05207322A - Serial/parallel converter for switching - Google Patents

Abstract

PURPOSE:To shorten the establishing time of a word synchronism by using the prescribed value in the vicinity of a switching timing. CONSTITUTION:A switching circuit 1 receives a switching control signal 12 from a switching control circuit 3 and selects and outputs arbitrary one signal from among plural serial TV signals 11 of a D2 format. A decoder 4 decodes data inserted once 1H and a decoder 5 decodes the prescribed value in the vicinity of the switching timing and generate reset pulses 14a and 14b. An AND circuit 6 receives the switching control signal 12 and the reset pulse 14b, outputs the reset pulse and an OR circuit 7 receives the reset pulse and the reset pulse 14a from the decoder 4 and outputs a result pulse 14 to a counter 8. The counter 8 outputs a word synchronizing pulse 15 to a serial/parallel conversion circuit 2. The serial/parallel conversion circuit 2 converts the serial TV signals 11 into parallel TV signals 13 synchronously with the word synchronizing pulse 15, and outputs them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a D2 format serial digital television video signal serial / parallel conversion device, and in particular, for switching which reduces switching shock in a D2 format serial digital television video signal. The present invention relates to a serial / parallel converter.

[0002]

2. Description of the Related Art Conventionally, when a plurality of synchronized D2 format serial digital television video signals (hereinafter referred to as serial TV signals) are switched, bit synchronization and word synchronization are deviated. As a method of establishing synchronization of word synchronization deviation, 3FF is added in the horizontal synchronization signal.
Signals such as (10 bits) and 000 (10 bits) have been inserted, and word synchronization has been established based on this signal. Therefore, it takes a maximum of 1H period to establish word synchronization.

FIG. 3 is a block diagram showing an example of such a conventional switching serial-parallel converter. In FIG. 3, 1 is a switching circuit that selectively outputs one serial TV signal 11 from a plurality of serial TV signals, and 2 is a parallel digital television video signal (hereinafter referred to as parallel TV signal) 13 that is the serial TV signal 11. A serial-parallel conversion circuit for converting to, and 3 is a switching circuit 1
Is a switching control circuit that outputs a switching control signal 12 to

[0004]

In the above-mentioned conventional switching serial-parallel conversion circuit, the word synchronization of the D2 format serial TV signal is not established for a maximum of 1H period until the word synchronization is established, and the succeeding device is not affected. Up to 1H
There was a drawback that it had a bad effect for a long time.

It is an object of the present invention to provide a switching serial-parallel conversion device which can shorten the time for establishing word synchronization by eliminating the above-mentioned drawbacks.

[0006]

According to the present invention, there is provided a switching control circuit for outputting a switching control signal, and a serial digital television video signal selectively selected from a plurality of serial digital television video signals by inputting the switching control signal. In the switching serial-parallel conversion device including a switching circuit that outputs a signal and a serial-parallel conversion circuit that converts and outputs the selected serial digital television video signal to a parallel digital television video signal, the selected serial A word synchronization establishment circuit for generating a word synchronization establishment pulse based on a digital television video signal and the switching control signal and outputting the pulse to the serial / parallel conversion circuit is provided.

Further, according to the present invention, the word synchronization establishing circuit inputs the selected serial digital television video signal, detects specific data contained in each of the serial digital television video signals, and detects a specified value in the vicinity of a switching timing. First and second decoders that output a second reset pulse, a logical product circuit that performs a logical product of the switching control signal and the second reset pulse, an output of the logical product circuit and the first It may include a logical sum circuit that takes a logical sum with the reset pulse, and a counter that inputs the output of the logical sum circuit to generate the word synchronization establishment pulse and outputs it to the serial-parallel conversion circuit.

[0008]

The word synchronization establishing circuit detects specific data for word synchronization in the serial TV signal selected by the switching circuit, outputs a word synchronization establishing pulse, and outputs the word synchronization establishing pulse near the switching timing in the serial TV signal. The specified value to be set is detected, and the word synchronization establishment pulse is output in accordance with the output of the switching control signal.

Therefore, it is not necessary to wait for 1H time for establishing the word synchronization, and it is possible to shorten the time for establishing the word synchronization.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In this embodiment, a switching control circuit 3 for outputting a switching control signal 12 and a single serial T signal 11 are selectively selected from a plurality of serial TV signals 11 by inputting the switching control signal 12.
A feature of the present invention is a switching serial-parallel conversion device that includes a switching circuit 1 that outputs a V signal and a serial-parallel conversion circuit 2 that converts and outputs the selected serial TV signal 11 into a parallel TV signal 13. However, the word synchronization establishing circuit 9 that generates the word synchronization pulse 15 based on the selected serial TV signal 11 and the switching control signal 12 and outputs the word synchronization pulse 15 to the serial / parallel conversion circuit 2 is provided.

Then, the word synchronization establishing circuit 9 inputs the selected serial TV signal 11 and detects the specific data contained in each of the serial TV signals 11 and the specified value in the vicinity of the switching timing for detecting the first data and the first value, respectively. A first and a second decoder (1) 4 and (2) 5 which output two reset pulses 14a and 14b, and an AND circuit 6 which obtains a logical product of the switching control signal 12 and the second reset pulse 14b. , The logical sum circuit 7 which takes the logical sum of the output of the logical product circuit 6 and the first reset pulse 14a
And a counter 8 which receives the output of the OR circuit 7 to generate a word synchronization pulse 15 and outputs it to the serial-parallel conversion circuit 2.

Next, the operation of this embodiment will be described with reference to the flow chart shown in FIG. The explanation is for data length 1
A case of 0 bit and a sampling frequency of 14.3 MHz will be described.

The D2 format serial TV signal 11 selected by the switching circuit 1 is input to the decoder (1) 4 (step S1). Decoder (1) 4 is 1 for 1H
The data inserted in the horizontal horizontal synchronizing signal is decoded and the reset pulse 14a is output (step S2). The reset pulse 14a is input to the counter 8 via the OR circuit 7 (step S5). The counter 8 operates at 143 MHz (14.3 MHz x 10 bits) and 1
When counting to 0, the word sync pulse 15 is output once (step S6). Serial-parallel conversion circuit 2
Is the D2 format serial TV signal 11 input from the switching circuit 1 based on the word synchronizing pulse 15.
The parallel TV signal 13 of two formats is converted (step S7).

Here, it is assumed that the switching circuit 1 switches the serial TV signal 11 in the D2 format. When switched, the serial TV signal 11 is out of bit synchronization and word synchronization. However, since the counter 8 outputs the word synchronization pulse 15 at the past pulse interval, the serial-parallel conversion is performed by the serial-parallel conversion circuit 2 for a maximum of 1H period while the word synchronization is deviated, and the serial-parallel conversion out of word synchronization is performed. Will be done.

However, a D2 format serial TV
Using the fact that the switching timing of the signal 11 is 4H or more after the vertical synchronizing signal and the data near the switching timing is regulated to 0F0 (10 bits) for a D2 format serial TV signal, the word synchronization establishment time is used. Can be shortened. The decoder (2) 5 receives the D2 format serial TV signal 11 output from the switching circuit 1.
Is also input (step S1). Decoder (2) 5 is 0
F0 (10 bits) is decoded and reset pulse 14b
Is output (step S3), the counter 8 is forcibly reset to switch the serial TV signal 11 in the D2 format after switching.
Establish word synchronization for. The OR circuit 7 is a circuit for outputting both the decoder (1) 4 and the decoder (2) 5 as a reset pulse 14 to the counter 8. In order to prevent the decoder (2) 5 from outputting the word synchronization reset pulse 14b outside the switching timing,
The logical product of the switching control signal 12 output from the switching control circuit 3 and the reset pulse 14b output from the decoder (2) 5 is taken by the logical product circuit 6 (step S4), and unnecessary word synchronization is performed outside the switching timing. The generation of the pulse 15 is prevented.

Although the present embodiment has been described in the case where the data length is 10 bits and the sampling frequency is 14.3 MHz, when the digital television signal is transmitted by using the specified value in the other formats as well. In addition, the specified value can be used to shorten the word synchronization establishment time in the same manner.

[0019]

As described above, the present invention has the effect of shortening the word synchronization establishment time by utilizing the specified value near the switching timing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 switching circuit 2 serial-parallel conversion circuit 3 switching control circuit 4 decoder (1) 5 decoder (2) 6 AND circuit 7 OR circuit 8 counter 11 serial TV signal 12 switching control signal 13 parallel TV signal 14, 14a, 14b reset Pulse 15 Word synchronization pulse S1 to S7 steps

Claims (2)

[Claims] 1. A switching control circuit which outputs a switching control signal, and a switching circuit which selectively outputs one serial digital television video signal from a plurality of serial digital television video signals by inputting the switching control signal, A serial / parallel conversion device for switching, which comprises a serial / parallel conversion circuit for converting and outputting the selected serial digital television video signal to a parallel digital television video signal, wherein the selected serial digital television video signal and the switching A switching serial-parallel conversion device comprising a word synchronization establishment circuit that generates a word synchronization establishment pulse based on a control signal and outputs the word synchronization establishment pulse to the serial-parallel conversion circuit. 2. The word synchronization establishing circuit inputs the selected serial digital television video signal, detects specific data included in the serial digital television video signal, and detects specified values near switching timing, and resets the first and second reset signals, respectively. First and second decoders for outputting pulses,
A logical product circuit for taking a logical product of the switching control signal and the second reset pulse, a logical sum circuit for taking a logical sum of the output of the logical product circuit and the first reset pulse, and a logical sum circuit 2. The switching serial-parallel conversion device according to claim 1, further comprising a counter which inputs the output of the above-mentioned, generates the word synchronization establishment pulse, and outputs the pulse to the serial-parallel conversion circuit.