JPH05147476A - Device for application treatment of vehicular control device - Google Patents

Abstract

PURPOSE: To realize a dual-port RAM function with a static RAM having a specific memory capacity by connecting a write/read memory, in a first cycle, to a control unit for reading out data, and by connecting the write/read memory, in a second cycle, to a series interface for reading in or reading out data. CONSTITUTION: A data-program-reading-out memory of a controller 14 is substituted by a data processor 22 having a RAM 10 and an operator console 19 is connected to the processor 22 via a series interface 16. A controlling unit 20 periodically switching a switching device 13 is provided and the RAM 10 is connected, in a first cycle, to the controller 14 for reading out data, and in a second cycle, to the interface 16 for reading in or writing data. The data in the RAM 10 varies in the operator console 19 during the operation of the controller 14. A large amount of memory density is available in the static RAM and a large dual-port-RAM enables emulation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for an automobile,
In particular, it relates to a device for application processing of an ignition control device and / or an injection control device.

[0002]

2. Description of the Prior Art For example, at a place where a control device for an ignition device, a fuel injection device, a skid control device, a steering device or the like of an automobile is installed,
In order to be able to be processed by a control unit with a high-speed microcontroller or microprocessor, the data / program read-out memory of the control unit, in the known form, is embodied as a general-purpose PROM or EPROM. It has been replaced by a normal replacement by the data processor. In this case, this data processing device is equipped with a read / write memory (RA
M) as a small piece of additional hardware. This write / read memory replaces the EPROM of the controller. In other words, the serial interface data and program values of the write / read memory can be fully converted via an operating device such as an operating computer. At the same time, the measurement data in digital form are transmitted via the same interface. This application process can in principle be used for any device equipped with a microprocessor.

In order to be able to carry out this data conversion during the operation of the control device, the known use device VS100-D1M of the applicant has two physically separated RAM banks. And conversions are performed between them. If the control device is located in the first RAM bank, only the second RAM bank can be accessed by the operating computer and vice versa. This form is relatively expensive and inflexible. However, it is also possible to use a so-called dual-port RAM instead of both RAM banks, so that they can be accessed by the outer side at the same time as the controller is running. However, for storage capacities of more than 64 kilobytes, which are necessary, for example, for reading out measured data or changing parameters, this kind of construction unit is not usable.

[0004]

The object of the present invention is to eliminate the abovementioned drawbacks.

[0005]

According to the present invention, the above-mentioned problems can be solved by the features of claim 1.

[0006]

The device according to the invention with the features of claim 1 can implement the function of a dual-port RAM with today's standard static RAM having a storage capacity of 1 megabit. It has the advantage of RA
Fault-free access to M is possible via the remote interface of the device via remote remote locations, for example from 5 m to 100 m each depending on the drive capacity. It is also defined that the dependence of physically separated RAM units on them is eliminated and that the partial areas of the RAM with various characteristics can be switched arbitrarily between them (eg write only, read only, Or read and write).

Another advantage resides in that the RAM memory can be configured as emulation memory from many arbitrary individual RAMs by simple parallel connection. This allows the number of pins of the data processing device to be kept low as long as they are formed as individual clips.

The entire mapping stored in RAM can be switched by means of a side switch, but also for individual parameters only, inside each active surface without a side switch. It can be changed.

All devices, especially data processing devices, require very few component parts. This has made it possible to achieve small dimensions and, as a result, to realize integration in a control device that is close to the series.

The withdrawal of the bus line from the data processor is not necessary due to the serial interface. This improves reliability, reduces the recurrence of failures, and improves the reliability of the new generation (for example, 80C196KR-16MH).
It became possible to use the high speed microcontroller of z). The control unit to be handled by the application is left in its original built-in position by fault-free access over distance. The switching of the serial application interfaces on the light guide then further improves the transmission rate and the safety of failures. This is particularly advantageous in test benches and test rooms.

Another advantage is that it can be used in different control devices with the same construction without the need for complicated adaptations. Furthermore, this structure can be freely used for different usage tasks such as parameter adjustment, EPROM switching, data detection, bypass calculation functions, etc.

The device according to the invention has the advantage of serial application (arbitrary length connection to the control device without failure).
And the advantages of parallel application to the controller via the EPROM interface (no additional software load on the controller computer due to the operation of the serial interface) are integrated as a whole.

The measures stated in the second and subsequent aspects realize another advantageous component of the device according to the first aspect.

This formation by the microprocessor is particularly advantageous when the control of the write-read memory is carried out by the multiplex bus controller. During each cycle, in the first phase, the address transmission is carried out by the data and in the second phase the reading or the reading is carried out by the data. Poor utilization of the bus bandwidth during multiplex operation is thereby improved in memory favorably for the second access.

A particularly space-saving arrangement of the data processing device is achieved by locating all the controls (except the memory) on one chip. This makes it possible in a simple manner to replace the data / program read-out memory of the control device in a simple manner, and also in the case of a control device close to a series or a control device in series. The chip is then preferably embodied as a programmable ASIC chip.

Another advantage is writing / writing on the data processing device.
It is caused by the parallel arrangement of the data / program read memory parallel to the read memory. The data / program read-out memory is then preferably EEPR.
It is configured as an OM. As a result, the data contents of both memories are command-controlled and the memories are exchanged with each other. For example, EEP by reset impulse
The contents of the ROM are now received in the write / read memory, which allows the preset to be performed. Conversely, emulated data is EEPRO
Can be protected in M.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention is illustrated in the drawings and will now be described in detail.

Write / read memory 10 (RAM) and data / program read memory 11 (EEPROM)
Are connected in parallel via the data / address bus 12. In the following, the expressions will be simplified and these will be referred to as RAM1.
0, EEPROM 11 and bus 12.
Instead of the EEPROM, it is possible in principle to replace it with the EPROM.

The bus 12 can be connected via the switching device 13 to either the control device 14 or the control unit 15 for the parallel interface 16. The switching device 13 is shown only schematically and may be realized in a known manner by gates, latches and multiplexers. Similarly, in principle, separate switching devices can be provided for the data bus and the address bus.

The control unit 14 is, for example, an ignition control unit and / or an injection control unit for a motor vehicle, which advantageously has a program read-out memory (PROM, EPROM or the like). Furthermore, the control device has a sensor inlet and a control outlet. However, the control unit 14 is shown for simplicity only as a block. Control unit 15 for serial interface 16
Are connected in a known manner to the required address counter or shift register 17 so that the incoming serial information can be converted into parallel address words. The serial interface 16 is a V-24 interface with a particularly high transmission rate (10 Mbit / s) or a Manchester type II (Manchester).
II) as a coded interface. An external operating device 19 is connected to the interface 16 via a serial conductor, and any computer can be used for the device 19.
The connection between the actuating device 19 and the serial interface 16 can also be made, for example via a light guide, so that a bridge can be created, especially if the distances are great.

A synchronization control unit 20 is further provided, and the unit 20 performs mutual access to the RAM 10.
And the serial interface 16 and its control unit 15 are synchronized by the temporal bus control of the control unit 14. For this reason, the components involved are connected via the required control conductors.

The purpose of all of these devices is to be able to carry out the application processing of the control unit 14 during its operation. That is, the mapping and programmatic data can be transformed or adapted with the help of the operating device 19. For this reason, the data / program read-out memory of the control unit 14 which is normally provided is isolated, the corresponding interface then being provided with the data processing constituted by the components 10 to 13, 15 to 17 and 20. The device 22 is connected. For this reason, the interface 21 may be designed as a plug-in socket, in which case only the read memory can be taken out and the data processing device 22 can be plugged into it. For this reason, the data processing device 22 includes the RAM 10 and the EEP.
Except ROM 11, for example, programmable AS
It is configured as a separate chip 23 such as an IC chip. Of course, it can also be realized as a multilayer structure or as a hybrid.

The mode of operation of the above-described device is essentially RAM1.
This is accomplished by replacing 0 with the original read memory of controller 14. The necessary program data and mapping are read in advance (in that case, a battery buffer is required), or the data content of the EEPROM 11 is changed to R by a start command.
It is either transmitted to AM10. Separately, the corresponding data is input to the operating device 19
There is also a possibility to read by.

During operation of the data processing device 22 and the control device 14, the synchronization control unit 20 switches the switching device 13 cyclically. In the first cycle, RAM10
Is connected to the controller 14 and its microcontroller reads data from the RAM 10 and in the next cycle the serial interface 16 can access the RAM 10 via its control unit 15 and there Either data reading or data writing or transcription is performed. Special time parameters must always be observed during this mutual access, which is ensured by the synchronization control unit 20. At first glance, in the case of this usage format, it seems that the RAM 10 can be used at least twice as fast. This is because it must be possible to double access to the same memory for its own write time or read time. However, in multiplex operation, this time issue is not important. This is because in this case the memory accesses are distributed in two phases. That is, in the first phase, the address is sent out,
In the second phase, data is being read or transmitted. The utilization of the bus bandwidth is not good in principle in the multiplex operation, but in this example, it is used for the second access on the memory.

In each of the second cycles, the operating device 1 is operated via the serial interface 16 and the control unit 15.
9 can be used to access the RAM 10, in which case its program data or the mapping is changed. In the following cycle, the already changed data is read by the control device 14 and, as a result, its operating characteristics are changed during the operation of this control device 14. During the second cycle, for example, the controller 14
Data such as the data measured by the sensor of RAM1
It is read and evaluated in the operating device 19 from 0.

In addition to individual data, the entire mapping and program area in RAM 10 is changed. As a result, fundamentally different driving characteristics can be tested directly before and after in time.

By using the EEPROM 11, it becomes possible to replace the newly changed data in the RAM 10 with the EEPROM 11 after the end of the emulation operation, and the data is protected. However, in a simple embodiment, the EEPROM 11 can also be omitted. It can in principle read the data in the operating device 19 or is a battery buffered RAM
This is because 10 can be used.

The synchronization control unit 20 is also used to translate the controller processor write commands into another area of the RAM 10. Due to this special write-only area, the stored data is read out at any time by the control unit 20 of the serial interface 16 and is further processed by the operating device 19 as measured data. This format simultaneously provides write protection for the read-only areas (program area and data area) of RAM 10.

[Brief description of drawings]

FIG. 1 is a block diagram showing the device of the present invention.

[Explanation of symbols]

 10 write / read memory 11 data / program read memory 12 data / address bus 13 switching device 14 control device 15 control unit 16 interface 17 address counter or shift register 18 serial conductor 19 operating device 20 synchronization control unit 22 data processing device 23 Tip

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Gujunter Hönigsich Federal Republic of Germany Dates Twingen Haldenschutlerse 88

Claims (11)

[Claims] 1. A device for application processing a control device for a motor vehicle, said device being at least 1.
It has one microprocessor and at least one data / program read memory (PROM, EPROM or the like), and a write / read memory (RA instead of the controller data / program read memory).
Control unit (20) for cyclically switching the switching device (13) in a type having a data processing device having M) and an operating device connectable via a serial interface A read / write memory (10) is connected via a switching device (13) to the control unit (14) for reading data in the first cycle and reading data in the second cycle. Or a device for application processing of a control unit for a motor vehicle, characterized in that it is connected to a serial interface (16) for reading. 2. A device for a microprocessor in a controller with a multiplex bus controller, comprising:
2. The apparatus according to claim 1, wherein during each cycle, address transmission is performed in the first phase and data reading or reading is performed in the second phase. 3. A Manchester type II coding device (M) with a serial interface (16) having a high transmission rate.
An apparatus according to claim 1 or 2, characterized in that it comprises an anchor II-Kodierung). 4. Device according to claim 1, characterized in that the entire control unit of the data processing device (22) is arranged on one chip (23). .. 5. Device according to claim 4, characterized in that the chip is configured as a programmable asic chip (ASIC-Chip). 6. A control unit (20) formed as a synchronization control unit is provided above the write / read memory (10) for controlling mutual access and also a serial interface (16). 6. Device according to claim 1, characterized in that a temporal bus control of the control device is provided for synchronization of the control device. 7. A data / program read memory (1
Device according to any one of claims 1 to 6, characterized in that 0) is connected in parallel to the write / read memory (10). 8. A data / program read memory (1
8. Device according to claim 7, characterized in that 1) is configured as an EEPROM. 9. The data contents of the write / read memory (10) and the data / program read memory (11) are:
9. The device according to claim 7, wherein the memories can be exchanged with each other in response to a command. 10. A write / read memory (10) provided for the control unit (20), which is embodied as a synchronization control unit, for converting the write commands of the microprocessor in the control unit (14). Device according to any one of claims 1 to 9, characterized in that it is provided in a special area of the. 11. The control unit (20), which is embodied as a synchronization control unit, is adapted to write / read memory (10) without accommodating a "wait state" during a read access of a microprocessor of the control device (14). Device according to any one of claims 1 to 10, characterized in that it is provided in such a way that mutual access to each other can be controlled.