JPH0511660B2 - - Google Patents

Info

Publication number
JPH0511660B2
JPH0511660B2 JP62078550A JP7855087A JPH0511660B2 JP H0511660 B2 JPH0511660 B2 JP H0511660B2 JP 62078550 A JP62078550 A JP 62078550A JP 7855087 A JP7855087 A JP 7855087A JP H0511660 B2 JPH0511660 B2 JP H0511660B2
Authority
JP
Japan
Prior art keywords
resin
island
integrated circuit
semiconductor chip
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62078550A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63244747A (ja
Inventor
Hiromichi Sawatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP62078550A priority Critical patent/JPS63244747A/ja
Priority to KR1019880003591A priority patent/KR910001419B1/ko
Publication of JPS63244747A publication Critical patent/JPS63244747A/ja
Priority to US07/506,251 priority patent/US5083189A/en
Publication of JPH0511660B2 publication Critical patent/JPH0511660B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
JP62078550A 1987-03-31 1987-03-31 樹脂封止型集積回路装置及びその製造方法 Granted JPS63244747A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62078550A JPS63244747A (ja) 1987-03-31 1987-03-31 樹脂封止型集積回路装置及びその製造方法
KR1019880003591A KR910001419B1 (ko) 1987-03-31 1988-03-31 수지봉합형 집적회로장치
US07/506,251 US5083189A (en) 1987-03-31 1990-04-09 Resin-sealed type IC device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62078550A JPS63244747A (ja) 1987-03-31 1987-03-31 樹脂封止型集積回路装置及びその製造方法

Publications (2)

Publication Number Publication Date
JPS63244747A JPS63244747A (ja) 1988-10-12
JPH0511660B2 true JPH0511660B2 (en:Method) 1993-02-16

Family

ID=13665025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62078550A Granted JPS63244747A (ja) 1987-03-31 1987-03-31 樹脂封止型集積回路装置及びその製造方法

Country Status (1)

Country Link
JP (1) JPS63244747A (en:Method)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2800761B2 (ja) * 1996-02-23 1998-09-21 日本電気株式会社 マルチチップ半導体装置
JP4965393B2 (ja) * 2007-08-30 2012-07-04 アスモ株式会社 樹脂封止型半導体装置
WO2010143379A1 (ja) * 2009-06-08 2010-12-16 パナソニック株式会社 電子部品実装構造体の製造方法および電子部品実装構造体
US9324639B2 (en) 2014-07-03 2016-04-26 Stmicroelectronics S.R.L. Electronic device comprising an improved lead frame
JP3243059U (ja) 2020-08-27 2023-08-02 ヒタチ・エナジー・スウィツァーランド・アクチェンゲゼルシャフト パワー半導体モジュールおよび製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120549U (en:Method) * 1975-10-20 1977-09-13
JPS6130067A (ja) * 1984-07-23 1986-02-12 Nec Kansai Ltd ハイブリツドｉｃ

Also Published As

Publication number Publication date
JPS63244747A (ja) 1988-10-12

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Legal Events

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