JPH049399B2 - - Google Patents
Info
- Publication number
- JPH049399B2 JPH049399B2 JP58029315A JP2931583A JPH049399B2 JP H049399 B2 JPH049399 B2 JP H049399B2 JP 58029315 A JP58029315 A JP 58029315A JP 2931583 A JP2931583 A JP 2931583A JP H049399 B2 JPH049399 B2 JP H049399B2
- Authority
- JP
- Japan
- Prior art keywords
- parts
- weight
- plating
- catalyst
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 40
- 239000003054 catalyst Substances 0.000 claims description 33
- 238000007747 plating Methods 0.000 claims description 28
- 229910052802 copper Inorganic materials 0.000 claims description 26
- 239000010949 copper Substances 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 20
- 229910000679 solder Inorganic materials 0.000 claims description 20
- 239000011889 copper foil Substances 0.000 claims description 15
- 230000003213 activating effect Effects 0.000 claims description 4
- 239000002518 antifoaming agent Substances 0.000 claims description 3
- 239000003086 colorant Substances 0.000 claims description 3
- 150000002357 guanidines Chemical class 0.000 claims description 3
- -1 epoxide compound Chemical class 0.000 claims description 2
- 239000000945 filler Substances 0.000 claims description 2
- 239000002904 solvent Substances 0.000 claims description 2
- 239000013008 thixotropic agent Substances 0.000 claims description 2
- 239000003822 epoxy resin Substances 0.000 claims 1
- 229920000647 polyepoxide Polymers 0.000 claims 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 238000007772 electroless plating Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- 239000012670 alkaline solution Substances 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- OAYXUHPQHDHDDZ-UHFFFAOYSA-N 2-(2-butoxyethoxy)ethanol Chemical compound CCCCOCCOCCO OAYXUHPQHDHDDZ-UHFFFAOYSA-N 0.000 description 1
- POAOYUHQDCAZBD-UHFFFAOYSA-N 2-butoxyethanol Chemical compound CCCCOCCO POAOYUHQDCAZBD-UHFFFAOYSA-N 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 239000004843 novolac epoxy resin Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical group Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 description 1
- IEQIEDJGQAUEQZ-UHFFFAOYSA-N phthalocyanine Chemical compound N1C(N=C2C3=CC=CC=C3C(N=C3C4=CC=CC=C4C(=N4)N3)=N2)=C(C=CC=C2)C2=C1N=C1C2=CC=CC=C2C4=N1 IEQIEDJGQAUEQZ-UHFFFAOYSA-N 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000454 talc Substances 0.000 description 1
- 229910052623 talc Inorganic materials 0.000 description 1
- HPGGPRDJHPYFRM-UHFFFAOYSA-J tin(iv) chloride Chemical compound Cl[Sn](Cl)(Cl)Cl HPGGPRDJHPYFRM-UHFFFAOYSA-J 0.000 description 1
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、銅張積層板を使用する印刷配線板の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a printed wiring board using a copper-clad laminate.
印刷配線板の製造は、絶縁基材に銅箔を有する
銅板積層板に貫通孔をあけ、エツチングによつて
回路形成を行ない、上記貫通孔部に無電解めつき
を施して、銅板積層板の裏表面に形成した回路を
接続することによつて行なわれている。
To manufacture printed wiring boards, through holes are made in a copper plate laminate having copper foil as an insulating base material, a circuit is formed by etching, and electroless plating is applied to the through holes to form a copper plate laminate. This is done by connecting a circuit formed on the back surface.
この製造方法において、貫通孔内に無電解めつ
きを施すには、この貫通孔内の絶縁壁に無電解銅
めつきの触媒を付与し、貫通孔内を活発性化する
工程が不可欠である。 In this manufacturing method, in order to perform electroless plating inside the through hole, a step of applying an electroless copper plating catalyst to the insulating wall inside the through hole to activate the inside of the through hole is essential.
通常用いられている上記貫通孔の活性化は、コ
ロイド状パラジユウム触媒中に印刷配線板を浸漬
することにより活性化処理されている。 The through holes are normally activated by immersing the printed wiring board in a colloidal palladium catalyst.
この活性化処理工程において、貫通孔以外の部
分、特に無電解めつきをを施さない部分への触媒
の付着を防止する必要がある。 In this activation treatment step, it is necessary to prevent the catalyst from adhering to parts other than the through holes, especially to parts not subjected to electroless plating.
従来の製造方法例えば特公昭46−39383号に開
示されている方法では、銅張積層板にエツチング
により所定の回路を形成し、貫通孔を設けた後
に、無電解用活性液（触媒）に浸漬して全表面を
活性化し、その後に貫通孔及びランド部を除く部
分、即ち無電解めつきをしない部分に耐めつきレ
ジストを塗布して、貫通孔とランド部を無電解め
つきしていたので、回路部分に触媒が残留し、絶
縁不良が生じ易いという技術的な問題があつた。 Conventional manufacturing methods For example, in the method disclosed in Japanese Patent Publication No. 46-39383, a predetermined circuit is formed on a copper-clad laminate by etching, through-holes are formed, and then immersed in an electroless active liquid (catalyst). After that, a plating resist was applied to the parts other than the through-holes and lands, that is, the parts not to be electrolessly plated, and the through-holes and lands were electrolessly plated. Therefore, there was a technical problem in that the catalyst remained in the circuit part and insulation defects were likely to occur.
この技術的な問題を解決した製造方法として、
特公昭48−27109号がある。 As a manufacturing method that solved this technical problem,
There is Special Publication No. 48-27109.
この製造方法は、銅張積層板にエツチングによ
り所定の回路を形成し、貫通孔を設けた基板の表
面にアルカリ可溶性ロジン変性樹脂の如き耐酸レ
ジストを印刷してから触媒中に浸漬して、活性化
する方法である。 This manufacturing method involves forming a predetermined circuit on a copper-clad laminate by etching, printing an acid-resistant resist such as an alkali-soluble rosin-modified resin on the surface of the substrate with through holes, and then immersing it in a catalyst to activate the circuit. This is a method of
この製造方法によれば、活性化後、アルカリ可
溶レジストをアルカリ溶液中で除去することによ
つて、回路間には触媒が残留せず、且つ貫通孔内
にのみ触媒を付着させることが可能となつた。 According to this manufacturing method, by removing the alkali-soluble resist in an alkaline solution after activation, no catalyst remains between the circuits, and it is possible to attach the catalyst only within the through-holes. It became.
しかしながら基板上への耐酸レジストの印刷
や、触媒中に浸漬した後の、アルカリ溶液中での
レジストの剥離の工程が増すためにその分の費用
がが印刷配線板の価格を上げ、製品価値を低下さ
せると共に、上記工数が増すことによつて量産に
対処することができないという問題があつた。 However, the additional costs of printing an acid-resistant resist on the board and stripping the resist in an alkaline solution after immersing it in a catalyst increase the price of the printed wiring board and reduce the product value. There was a problem in that it was not possible to cope with mass production due to the increase in the number of man-hours.
また、上記の製造法で用いる耐めつきレジスト
は、ランド、スルーホール部以外の導体部分をマ
スクし、めつき面積を減少するのが目的であつ
た。このような耐めつきレジストでは、めつき中
に耐めつきレジストを塗布した銅箔上に腐食を生
じるために、ソルダレジストとして使用すること
はできなかつた。したがつて、めつき後耐めつき
レジストを除去し、再度通常のソルダレジストを
塗布する必要があり、回路板価格増加の要因とな
つていた。 Furthermore, the purpose of the plating resist used in the above manufacturing method was to mask the conductor portions other than the land and through-hole portions, thereby reducing the plating area. Such a plating resist cannot be used as a solder resist because corrosion occurs on the copper foil coated with the plating resist during plating. Therefore, after plating, it is necessary to remove the plating resist and reapply a normal solder resist, which has been a factor in increasing the price of the circuit board.
本発明は上記従来の問題を鑑みなされたもので
あり、量産性、信頼性に優れ、実装密度の良い低
コストの印刷配線板を製造する方法を提供しよう
とするものである。
The present invention has been made in view of the above-mentioned conventional problems, and it is an object of the present invention to provide a method for manufacturing a low-cost printed wiring board with excellent mass productivity, reliability, and good packaging density.
即ち、本発明は次の〜の工程の工程順に製
造することを特徴とする多層印刷配線板の製造方
法。
That is, the present invention is a method for producing a multilayer printed wiring board, characterized in that the production is performed in the order of the following steps.
銅張積層板の所定位置に貫通孔をあけ、穴あ
き銅張積層板とする工程
上記穴あき銅張積層板の表面及び貫通孔の内
壁を触媒で活性化する工程
ランド部と配線回路部を除く銅箔の不要部分
をエツチングにより除去し、貫通孔の内壁のみ
触媒で活性化された回路基板とする工程
上記回路基板の貫通孔の内壁及びランド部の
銅箔全表面が露出するように、貫通孔の内壁及
びランド部の銅箔全表面以外の配線回路部の表
面に耐めつきソルダレジストを付着する工程
上記貫通孔の内壁及びランド部の銅箔全表面
に無電解銅めつきを施す工程
〔発明の実施例〕
以下本発明の一実施例について詳細に説明す
る。先ず第１の実施例について第１図を用いて説
明する。第１図ａ〜ｈは印刷配線板の製造工程を
工程順に示したものである。 A process of making through holes at predetermined positions in the copper clad laminate to form a perforated copper clad laminate A process of activating the surface of the perforated copper clad laminate and the inner walls of the through holes with a catalyst A process of activating the land portion and the wiring circuit portion A step of removing unnecessary parts of the copper foil by etching to make a circuit board in which only the inner wall of the through hole is activated with a catalyst. A process of attaching a plating-resistant solder resist to the surface of the wiring circuit section other than the inner wall of the through hole and the entire surface of the copper foil in the land area. Electroless copper plating is applied to the inner wall of the through hole and the entire surface of the copper foil in the land area. Process [Embodiment of the Invention] An embodiment of the present invention will be described in detail below. First, a first embodiment will be explained using FIG. 1. FIGS. 1a to 1h show the manufacturing process of a printed wiring board in order of process.
第１図ａにおいて、１が銅張積層板の基材であ
り、この基材１の両面に18乃至35μm厚さの銅箔
２を設け、銅張積層板を構成する。次に、第１図
ｂにおいて、この銅張積層板の所定の位置に貫通
孔３をあける。次に、第１図ｃにおいて、このよ
うな貫通孔３をあけた穴あけ銅張積層板を無電解
銅めつき用触媒に浸漬し、銅張積層板の表面及び
貫通孔３の内壁に触媒４を付着させる。 In FIG. 1a, 1 is a base material of a copper-clad laminate, and copper foil 2 with a thickness of 18 to 35 μm is provided on both sides of this base material 1 to constitute a copper-clad laminate. Next, as shown in FIG. 1b, through holes 3 are drilled at predetermined positions in this copper-clad laminate. Next, in FIG. 1c, the perforated copper clad laminate with such through holes 3 is immersed in a catalyst for electroless copper plating, and the catalyst 4 is applied to the surface of the copper clad laminate and the inner wall of the through hole 3. Attach.
ここに使用する触媒液は、塩化パラジユウム、
塩化スズ系の通常工業的に使用されるコロイド状
触媒もしくはアルカリ性パラジユウム触媒を用い
る。但しアルカリ性パラジユウム触媒を用いる場
合は、付着させた後、触媒を還元する必要があ
る。 The catalyst liquid used here is palladium chloride,
A colloidal catalyst based on tin chloride or an alkaline palladium catalyst, which is commonly used industrially, is used. However, when using an alkaline palladium catalyst, it is necessary to reduce the catalyst after it is deposited.
市販されているもので容易に入手できるものと
しては、前者はシツプレイ44、後者はシエーリン
グネオガント834をあげることができる。 Commercially available products that are easily available include Shitsuprey 44 for the former and Schering Neo Gant 834 for the latter.
さて、触媒を付着させた後、第１図ｄにおい
て、銅張積層板上の回路及びランドとなる部分
に、エツチングレジスト５を塗布する。その後、
第１図ｅにおいて、不要の銅箔をエツチングして
除去すると同時に、その部分の触媒４も除去し、
基板６を形成する。 After the catalyst has been deposited, an etching resist 5 is applied to the portions of the copper clad laminate that will become circuits and lands, as shown in FIG. 1d. after that,
In FIG. 1e, the unnecessary copper foil is etched and removed, and at the same time, the catalyst 4 in that area is also removed.
A substrate 6 is formed.
この時使用するエツチングレジスト５，エツチ
ング液は市販されているものでもよい。 The etching resist 5 and etching solution used at this time may be commercially available.
次に第１図ｆにおいて、上記基板６のエツチン
グレジスト５を除去し、回路基板７とする。その
後、第１図ｇにおいて、回路基板の貫通孔３の内
壁及びランド部の表面を除く配線回路部の表面に
耐めつきソルダレジスト８を付着する。この耐め
つきソルダレジスト８は、無電解銅めつきにより
下地の基板、回路パターンとの密着性が低下せ
ず、且つソルダレジストとしても使用可能な特性
を備えたものを使用する。この耐めつきソルダレ
ジストは、エポキサイド化合物（フエノールノボ
ラツクエポキシ樹脂、例えばエピコート152，
154；シエル化学製）100重量部に対し、グアニジ
ン誘導体（例えば１−０−トリルビグアニドもし
くはその変成物）２〜40重量部、充てん剤（例え
ばタルクもしくは石英粉末３〜40重量部、揺変剤
（微粉末シリカ、例えばアエロジルA380）２〜20
重量部、消泡剤（例えばシリコーン消泡剤、
SH5540；トーレシリコーン製）0.5〜20量部、着
色剤（例えばフタロシアニングリーン）0.5〜５
重量部、溶剤（例えばｎ−ブチルカルビトールも
しくはブチルセロソルブ）５〜30重量部よりなる
ものである。 Next, in FIG. 1f, the etching resist 5 of the substrate 6 is removed to form a circuit board 7. Thereafter, in FIG. 1g, a solder resist 8 is applied to the surface of the wiring circuit section except for the inner wall of the through hole 3 of the circuit board and the surface of the land section. This plating-resistant solder resist 8 is one that does not deteriorate its adhesion to the underlying substrate and circuit pattern due to electroless copper plating, and has characteristics that it can also be used as a solder resist. This solder resist is made of epoxide compounds (phenol novolac epoxy resins, such as Epicoat 152,
154 (manufactured by Ciel Chemical), 2 to 40 parts by weight of a guanidine derivative (for example, 1-0-tolylbiguanide or a modified product thereof), a filler (for example, 3 to 40 parts by weight of talc or quartz powder), and a thixotropic agent. (Fine powder silica, e.g. Aerosil A380) 2-20
parts by weight, antifoaming agent (e.g. silicone antifoaming agent,
SH5540; manufactured by Toray Silicone) 0.5 to 20 parts, colorant (e.g. phthalocyanine green) 0.5 to 5
parts by weight, and 5 to 30 parts by weight of a solvent (for example, n-butyl carbitol or butyl cellosolve).
次いで、第１図ｈにおいて、貫通孔３の内壁と
ランド部の表面に無電解銅めつき９を施す。 Next, as shown in FIG. 1h, electroless copper plating 9 is applied to the inner wall of the through hole 3 and the surface of the land portion.
以上において、本発明の特徴は特に、配線回路
部の触媒を不要な銅箔と共にエツチング除去する
第１図ｅの工程（前記の工程）と、回路基板の
貫通孔の内壁とランド部の表面を除いた配線回路
部の表面に耐めつきソルダレジストを付着する第
１図ｇの工程（前記の工程）にある。 In the above, the features of the present invention are particularly the step shown in FIG. The step shown in FIG. 1g (the above-mentioned step) is in which a solder resist is applied to the surface of the removed wiring circuit section.
即ち、この製造方法により上記耐めつきソルダ
レジストが第１図ｈの無電解銅めつきの工程以後
の工程や部品搭載後も基板から剥離することな
く、更にランド部の全表面に無電解銅めつきの付
着を可能とし、スルーホール部はんだ接続面積の
確保と信頼性の向上を可能としたものである。こ
れにより量産性、歩留まり、信頼性が良く、か
つ、実装密度が向上した印刷配線板を提供するこ
とができる。 That is, with this manufacturing method, the above-mentioned plating-resistant solder resist does not peel off from the board even after the electroless copper plating step shown in FIG. This makes it possible to secure the solder connection area of the through-hole part and improve reliability. This makes it possible to provide a printed wiring board with good mass productivity, yield, and reliability, and with improved packaging density.
次に第２の実施例について第２図を用い説明す
る。第２図ａ〜ｈは、第１図と同様に、製造工程
順に示す。 Next, a second embodiment will be explained using FIG. 2. Similar to FIG. 1, FIGS. 2a to 2h are shown in the order of manufacturing steps.
第２図ａにおいて、１０は前記第１の実施例と
同様の銅張積層板の基材あり、この基材１０の両
面に、18乃至35μmの厚さの銅箔を設け、銅板積
層板を構成する。次に第２図ｂにおいて、この銅
張積層板の所定の位置に貫通孔１１をあけ、第２
図ｃにおいて、回路部及びランド部にエツチング
レジスト１２の塗布する。次に第２図ｄにおい
て、これを第１の実施例と同様の触媒液に浸漬
し、穴あき銅張積層板の表面及び貫通孔１１の内
壁に触媒１３を付着させる。 In FIG. 2a, reference numeral 10 denotes a base material of a copper-clad laminate similar to that of the first embodiment. Copper foil with a thickness of 18 to 35 μm is provided on both sides of this base material 10, and a copper plate laminate is formed. Configure. Next, in FIG. 2b, a through hole 11 is drilled at a predetermined position in this copper clad laminate, and a second
In FIG. c, an etching resist 12 is applied to the circuit portion and the land portion. Next, in FIG. 2d, this is immersed in the same catalyst solution as in the first embodiment, and the catalyst 13 is attached to the surface of the perforated copper-clad laminate and the inner wall of the through hole 11.
ここで注意すべきことは、触媒液のPHが酸性か
ら中性の場合には、エツチングレジストにアルカ
リ可溶性のレジストを使用できるが、触媒液がア
ルカリ性の場合には、エツチングレジストには有
機溶剤可溶性のレジストが適している。 It should be noted here that if the pH of the catalyst solution is acidic to neutral, an alkali-soluble etching resist can be used, but if the catalyst solution is alkaline, an organic solvent-soluble etching resist can be used. Resist is suitable.
これらのレジストは、市販品として入手でき、
前者の例として山栄化学SER400、後者の例とし
て山栄化学SPR550があげられる。 These resists are commercially available;
An example of the former is Sanei Chemical SER400, and an example of the latter is Sanei Chemical SPR550.
さて、上記のように触媒を付着させた後、第２
図ｅにおいて、エツチングして不要の銅箔を除去
すると同時にその部分の触媒も同時に除去して１
４とし、次いで、第２図ｆにおいて、エツチング
レジスト１２を上記した特性に従つてアルカリ溶
液もしくは、塩化メチレン等の有機溶剤で除去
し、貫通孔１１のみを活性化した回路基板１５と
する。このように貫通孔１１のみを活性化した回
路基板１５に、第２図ｇにおいて、前記第１の実
施例と同じように貫通孔の内壁及びランド部の表
面を除く配線回路部の表面に耐めつきソルダーレ
ジスト１６を付着し、次いで、第２図ｈにおい
て、前記第１の実施例と同じように無電解銅めつ
き１７をし、印刷配線板が完成される。 Now, after attaching the catalyst as described above, the second
In Figure e, when removing unnecessary copper foil by etching, the catalyst in that area is also removed at the same time.
4, and then, as shown in FIG. 2f, the etching resist 12 is removed with an alkaline solution or an organic solvent such as methylene chloride in accordance with the above-mentioned characteristics to form a circuit board 15 with only the through holes 11 activated. In FIG. 2g, on the circuit board 15 with only the through-holes 11 activated, the surfaces of the wiring circuit parts except the inner walls of the through-holes and the surfaces of the land parts are coated with resistance, as in the first embodiment. A plating solder resist 16 is deposited, and then, as shown in FIG. 2h, electroless copper plating 17 is applied in the same manner as in the first embodiment to complete the printed wiring board.
この製造方法も、前記第１の実施例と同様に、
上記耐めつきソルダレジストが第１図ｈの無電解
めつきの工程以後の工程や部品搭載後も基板から
剥離することなく、更にランド部の全表面に無電
解銅めつきの付着を可能とし、スルーホール部は
んだ接続面積の確保と信頼性の向上を可能とした
ものである。これにより量産性、歩留まり、信頼
性が良く、かつ、実装密度が向上した印刷配線板
を提供することができる。 This manufacturing method is also similar to the first embodiment,
The above-mentioned plating-resistant solder resist does not peel off from the board even after the electroless plating process shown in Fig. 1 h or after mounting components, and it also enables electroless copper plating to adhere to the entire surface of the land area, allowing through-the-hole copper plating. This makes it possible to secure the solder connection area of the hole part and improve reliability. This makes it possible to provide a printed wiring board with good mass productivity, yield, and reliability, and with improved packaging density.
以上詳述した通り、本発明による印刷配線板の
製造方法の特徴は特に、配線回路間の触媒を不面
な銅箔と共にエツチング除去する工程と、貫通孔
の内壁とランド部表面を除く配線回路部の表面に
耐めつきソルダレジストを塗布する工程にあり、
本発明の印刷配線板の製造方法により、上記耐め
つきソルダレジストが無電解銅めつきの工程以後
の工程や部品搭載も基板から剥離することなく、
更にランド部の全表面に無電解銅めつきの付着を
可能とし、スルーホール部はんだ接続面積の確保
と信頼性の向上を可能としたものである。そし
て、本発明により量産性、歩留まり、信頼性が良
く、かつ、実装密度が向上した印刷配線板を提供
することができる効果を奏する。
As detailed above, the method for manufacturing a printed wiring board according to the present invention is particularly characterized by the step of etching away the catalyst between the wiring circuits together with the unfavorable copper foil, and the process of etching away the catalyst between the wiring circuits together with the unfavorable copper foil, and the wiring circuits excluding the inner wall of the through hole and the surface of the land portion. In the process of applying a resistant solder resist to the surface of the part,
According to the method of manufacturing a printed wiring board of the present invention, the above-mentioned anti-metal solder resist does not peel off from the board during the steps after the electroless copper plating process and when mounting components.
Furthermore, it is possible to apply electroless copper plating to the entire surface of the land portion, thereby making it possible to secure the solder connection area of the through-hole portion and improve reliability. Further, the present invention has the effect of being able to provide a printed wiring board with good mass productivity, high yield, and reliability, and with improved packaging density.
第１図及び第２図共に本発明の一実施例であ
り、第１図ａ〜ｈは貫通孔をあけた後に触媒中に
浸漬し、その後エツチングレジストを塗布した場
合の実施例であり、又第２図ａ〜ｈは、貫通孔を
あけた後エツチングレジストを塗布しその後触媒
中に浸漬してエツチングする場合の実施例を示
し、第１図及び第２図共に製造工程順にその要部
を断面して示した図である。
１…銅板積層板の基板、２…銅箔、３，１１…
貫通孔、４，１３…触媒、５，１２…エツチング
レジスト、８，１６…耐めつきソルダ−レジス
ト、９，１７…無電解めつき。
Both Figures 1 and 2 are examples of the present invention, and Figures 1a to 1h are examples in which the through holes are drilled, then immersed in the catalyst, and then an etching resist is applied. Figures 2a to 2h show an example in which an etching resist is applied after drilling a through hole and then immersed in a catalyst for etching, and both Figures 1 and 2 show the main parts in the order of the manufacturing process. It is a cross-sectional view. 1... Substrate of copper plate laminate, 2... Copper foil, 3, 11...
Through hole, 4, 13... Catalyst, 5, 12... Etching resist, 8, 16... Plating resistant solder resist, 9, 17... Electroless plating.
Claims (1)
特徴とする多層印刷配線板の製造方法。 銅張積層板の所定位置に貫通孔をあけ、穴あ
き銅張積層板とする工程 上記穴あき銅張積層板の表面及び貫通孔の内
壁を触媒で活性化する工程 ランド部と配線回路部を除く銅箔の不要部分
をエツチングにより除去し、貫通孔の内壁のみ
触媒で活性化された回路基板とする工程 上記回路基板の貫通孔の内壁及びランド部の
銅箔全表面が露出するように、貫通孔の内壁及
びランド部の銅箔全表面以外の配線回路部の表
面に耐めつきソルダレジストを付着する工程 上記貫通孔の内壁及びランド部の銅箔全表面
に無電解銅めつきを施す工程 ２ 上記特許請求の範囲第１項の多層印刷配線板
の製造方法において、の工程の耐めつきソルダ
レジストが、グアニジン誘導体含有エポキシ樹脂
よりなることを特徴とする印刷配線板の製造方
法。 ３ 上記特許請求の範囲第１項の多層印刷配線板
の製造方法において、の工程の耐めつきソルダ
レジストが、エポキサイド化合物100重量部に対
し、グアニジン誘導体２〜40重量部、充てん剤３
〜40重量部、揺変剤２〜20重量部、消泡剤0.5〜
20重量部、着色剤0.5〜５重量部、溶剤５〜30重
量部よりなることを特徴とする印刷配線板の製造
方法。[Scope of Claims] 1. A method for producing a multilayer printed wiring board, characterized in that the production is performed in the order of the following steps. A process of making through holes at predetermined positions in the copper clad laminate to form a perforated copper clad laminate A process of activating the surface of the perforated copper clad laminate and the inner walls of the through holes with a catalyst A process of activating the land portion and the wiring circuit portion A step of removing unnecessary parts of the copper foil by etching to make a circuit board in which only the inner wall of the through hole is activated with a catalyst. A process of attaching a plating-resistant solder resist to the surface of the wiring circuit section other than the inner wall of the through hole and the entire surface of the copper foil in the land area. Electroless copper plating is applied to the inner wall of the through hole and the entire surface of the copper foil in the land area. Step 2: The method for manufacturing a multilayer printed wiring board according to claim 1, wherein the solder resist in step 2 is made of an epoxy resin containing a guanidine derivative. 3. In the method for manufacturing a multilayer printed wiring board according to claim 1 above, the plating-resistant solder resist in the step contains 2 to 40 parts by weight of a guanidine derivative and 3 parts by weight of a filler based on 100 parts by weight of an epoxide compound.
~40 parts by weight, thixotropic agent 2-20 parts by weight, antifoaming agent 0.5~
20 parts by weight of a colorant, 0.5 to 5 parts by weight of a colorant, and 5 to 30 parts by weight of a solvent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2931583A JPS59155994A (en) | 1983-02-25 | 1983-02-25 | Method of producing printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2931583A JPS59155994A (en) | 1983-02-25 | 1983-02-25 | Method of producing printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59155994A JPS59155994A (en) | 1984-09-05 |
| JPH049399B2 true JPH049399B2 (en) | 1992-02-20 |
Family
ID=12272782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2931583A Granted JPS59155994A (en) | 1983-02-25 | 1983-02-25 | Method of producing printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59155994A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6066899A (en) * | 1983-09-22 | 1985-04-17 | 日本電気株式会社 | Method of producing printed circuit board |
| JPS61176187A (en) * | 1985-01-31 | 1986-08-07 | エルナ−株式会社 | Manufacture of printed wiring board |
| JPS6392089A (en) * | 1986-10-06 | 1988-04-22 | イビデン株式会社 | Printed wiring board and manufacture of the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5088557A (en) * | 1973-12-10 | 1975-07-16 | ||
| JPS569032A (en) * | 1979-07-03 | 1981-01-29 | Natl House Ind Co Ltd | Production of brace |
| JPS5771199A (en) * | 1980-10-22 | 1982-05-01 | Hitachi Ltd | Method of fabricating circuit board |
| JPS5790072A (en) * | 1980-11-25 | 1982-06-04 | Hitachi Ltd | Resist ink composition for chemical plating |
| JPS59147487A (en) * | 1983-02-14 | 1984-08-23 | 株式会社日立製作所 | Method of producing printed circuit board |
-
1983
- 1983-02-25 JP JP2931583A patent/JPS59155994A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5088557A (en) * | 1973-12-10 | 1975-07-16 | ||
| JPS569032A (en) * | 1979-07-03 | 1981-01-29 | Natl House Ind Co Ltd | Production of brace |
| JPS5771199A (en) * | 1980-10-22 | 1982-05-01 | Hitachi Ltd | Method of fabricating circuit board |
| JPS5790072A (en) * | 1980-11-25 | 1982-06-04 | Hitachi Ltd | Resist ink composition for chemical plating |
| JPS59147487A (en) * | 1983-02-14 | 1984-08-23 | 株式会社日立製作所 | Method of producing printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59155994A (en) | 1984-09-05 |
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