JPS61176187A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPS61176187A
JPS61176187A JP1762785A JP1762785A JPS61176187A JP S61176187 A JPS61176187 A JP S61176187A JP 1762785 A JP1762785 A JP 1762785A JP 1762785 A JP1762785 A JP 1762785A JP S61176187 A JPS61176187 A JP S61176187A
Authority
JP
Japan
Prior art keywords
hole
forming
printed wiring
copper
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1762785A
Other languages
Japanese (ja)
Inventor
佐治 勝信
隆之 赤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elna Co Ltd
Original Assignee
Elna Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elna Co Ltd filed Critical Elna Co Ltd
Priority to JP1762785A priority Critical patent/JPS61176187A/en
Publication of JPS61176187A publication Critical patent/JPS61176187A/en
Pending legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [発明の技術分野] この発明はプリント配線板の製造方法に関し。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method of manufacturing a printed wiring board.

さらに詳しく言えば、無電解銅めっきによるスルーホー
ルめっきプリント配線板の製造方法に関するものである
More specifically, the present invention relates to a method of manufacturing a through-hole plated printed wiring board by electroless copper plating.

〔発明の技術的背景] 従来、スルーホールめっきプリント配線板の多くは、電
気鋼めっきによる方法で製造されている。
[Technical Background of the Invention] Conventionally, many through-hole plated printed wiring boards have been manufactured by an electric steel plating method.

しかしながら、電気鋼めっきによる製造方法は、大量生
産が困難であり、コストが高く、シかも工程が長くなる
という点に問題がある。
However, the manufacturing method using electric steel plating has problems in that mass production is difficult, the cost is high, and the process may be long.

[発明の目的] この発明は上記した電気鋼めっき法の欠点に鑑みなされ
たもので、その目的は、比較的簡単かつ短かい工程によ
り、品質の安定したスルーホールめっきプリント配線板
を大量生産し得る製造方法を提供することにある。
[Object of the invention] This invention was made in view of the above-mentioned drawbacks of the electric steel plating method, and its purpose is to mass-produce through-hole plated printed wiring boards with stable quality through a relatively simple and short process. The purpose is to provide a manufacturing method that obtains the desired results.

[実 施 例] 以下、この発明を第1図に示されている一実施例を参照
しながら詳細に説明する。
[Example] Hereinafter, the present invention will be described in detail with reference to an example shown in FIG.

まず、第1図(A)に示すように、絶縁基体1の表裏に
銅箔2a、2bを接触してなる銅張積層板3を用意し、
スルーホールを形成する部分に同図(B)に示すように
ドリル加工またはパンチング加工により透孔4を形成す
る。次に、活性化処理し、銅箔2a、2bの表面および
透孔4内に同図(C)に点線で示すように無電解銅めっ
きの活性液5、感光性フィルム7.7により密封してそ
の孔壁を保護するとともに、銅張積層板3の表裏の所要
箇所に回路パターン形成のためのエツチングレジストを
形成する。なお、感光性フィルムに代えてインク孔埋め
印刷法等により孔壁を保護することもできる。エツチン
グ処理後、同図(E)に示すように上記の感光性フィル
ム7.7およびエツチングレジストを剥離し、回路パタ
ーンを保護するための永久レジスト8を同図(F)に示
すように形成する。この永久レジスト8は次工程のめっ
き処理のめっきレジストおよび電気部品の実装時のハン
ダレジストの機能を果すものである0次いで永久レジス
ト8の形成されていない箇所、同図(G)では透孔4の
両端およびその孔壁内に無電解銅めっき、つまり部分め
っきを施し、析出銅層9を形成する。
First, as shown in FIG. 1(A), a copper-clad laminate 3 is prepared by contacting copper foils 2a and 2b on the front and back sides of an insulating substrate 1,
A through hole 4 is formed in the portion where the through hole is to be formed by drilling or punching, as shown in FIG. 3(B). Next, the surfaces of the copper foils 2a, 2b and the through holes 4 are sealed with an active liquid 5 for electroless copper plating and a photosensitive film 7.7 as shown by dotted lines in FIG. In addition to protecting the hole walls, an etching resist for forming a circuit pattern is formed at required locations on the front and back sides of the copper-clad laminate 3. Note that instead of using a photosensitive film, the pore walls can also be protected by an ink hole-filling printing method or the like. After the etching process, the photosensitive film 7.7 and the etching resist are peeled off as shown in Figure (E), and a permanent resist 8 for protecting the circuit pattern is formed as shown in Figure (F). . This permanent resist 8 functions as a plating resist in the next plating process and as a solder resist when mounting electrical components. Electroless copper plating, that is, partial plating, is applied to both ends of the hole and inside the hole wall to form a deposited copper layer 9.

上記した実施例の説明から明らかなように、この発明に
よれば、無電解めっき法によりスルーホールを形成する
ようにしたことにより、均一なめつき厚が得られ、しか
も大量生産が可能で大幅なコスト低減が図れるとともに
、銅張積層板を材料とすることから安定した回路形成と
強い銅箔密着力により高精度、高品質のスルーホールめ
っきプリント配線板を製造することが可能となる。
As is clear from the description of the embodiments described above, according to the present invention, by forming through holes by electroless plating, a uniform plating thickness can be obtained, mass production is possible, and a large amount of In addition to reducing costs, since the copper-clad laminate is used as a material, stable circuit formation and strong copper foil adhesion make it possible to manufacture high-precision, high-quality through-hole plated printed wiring boards.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(A)〜(G)図はこの発明を説明するための工
程図である。 図中、1は絶縁基体、2a、2bは銅箔、3は銅張積層
板、4は透孔、5は活性液、7は感光性フィルム、8は
永久レジスト、9は析出鋼層である。
FIGS. 1A to 1G are process diagrams for explaining the present invention. In the figure, 1 is an insulating substrate, 2a and 2b are copper foils, 3 is a copper-clad laminate, 4 is a through hole, 5 is an active liquid, 7 is a photosensitive film, 8 is a permanent resist, and 9 is a precipitated steel layer. .

Claims (1)

【特許請求の範囲】[Claims] 銅張積層板に透孔を形成する工程と、上記透孔の孔壁を
含む上記銅張積層板の全面に活性化処理により無電解銅
めっきの活性核を析出する工程と、感光性フィルム等の
保護手段にて上記透孔の孔壁を保護するとともに、所定
の回路パターンを保護するエッチングレジストを形成す
る工程と、エッチング処理して所定の回路パターンを形
成する工程と、永久レジストを形成するとともに上記保
護手段を除去して上記透孔の孔壁に無電解銅めっき処理
により析出銅層を形成する工程とを含んでなるプリント
配線板の製造方法。
a step of forming through holes in the copper clad laminate; a step of depositing active nuclei of electroless copper plating on the entire surface of the copper clad laminate including the walls of the through holes by activation treatment; and a photosensitive film, etc. a step of forming an etching resist that protects the hole wall of the through hole and a predetermined circuit pattern with a protective means; a step of etching to form the predetermined circuit pattern; and a step of forming a permanent resist. and the step of removing the protective means and forming a deposited copper layer on the wall of the through hole by electroless copper plating.
JP1762785A 1985-01-31 1985-01-31 Manufacture of printed wiring board Pending JPS61176187A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1762785A JPS61176187A (en) 1985-01-31 1985-01-31 Manufacture of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1762785A JPS61176187A (en) 1985-01-31 1985-01-31 Manufacture of printed wiring board

Publications (1)

Publication Number Publication Date
JPS61176187A true JPS61176187A (en) 1986-08-07

Family

ID=11949101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1762785A Pending JPS61176187A (en) 1985-01-31 1985-01-31 Manufacture of printed wiring board

Country Status (1)

Country Link
JP (1) JPS61176187A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01256193A (en) * 1988-04-06 1989-10-12 Oki Densen Kk Manufacture of small diameter through hole substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59155994A (en) * 1983-02-25 1984-09-05 株式会社日立製作所 Method of producing printed circuit board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59155994A (en) * 1983-02-25 1984-09-05 株式会社日立製作所 Method of producing printed circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01256193A (en) * 1988-04-06 1989-10-12 Oki Densen Kk Manufacture of small diameter through hole substrate

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