JPH048984U - - Google Patents

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Publication number
JPH048984U
JPH048984U JP4944090U JP4944090U JPH048984U JP H048984 U JPH048984 U JP H048984U JP 4944090 U JP4944090 U JP 4944090U JP 4944090 U JP4944090 U JP 4944090U JP H048984 U JPH048984 U JP H048984U
Authority
JP
Japan
Prior art keywords
stage
circuit
light
logical product
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4944090U
Other languages
Japanese (ja)
Other versions
JPH0749428Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990049440U priority Critical patent/JPH0749428Y2/en
Priority to DE69125522T priority patent/DE69125522T2/en
Priority to EP96114375A priority patent/EP0753939A1/en
Priority to EP91304150A priority patent/EP0456482B1/en
Priority to US07/697,894 priority patent/US5099113A/en
Publication of JPH048984U publication Critical patent/JPH048984U/ja
Application granted granted Critical
Publication of JPH0749428Y2 publication Critical patent/JPH0749428Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第3図は請求項(1)に記載した考案に
係る実施例のそれぞれブロツク図、要部の回路図
、および回路中の各点における信号波形のタイミ
ングチヤートである。また、第4図〜第6図は請
求項(2)に記載した考案に係る実施例のそれぞれ
ブロツク図、要部の回路図、および回路図中の各
点における信号波形のタイミングチヤートである
。 3……投光回路、4……受光回路、8……信号
処理回路、13〜17……JKフリツプフロツプ
、20〜22,24〜26……AND回路、19
……AND回路(セツト出力論理積手段)、23
……AND回路(リセツト出力論理積手段)。
1 to 3 are a block diagram, a circuit diagram of essential parts, and a timing chart of signal waveforms at each point in the circuit, respectively, of an embodiment according to the invention described in claim (1). 4 to 6 are a block diagram, a circuit diagram of a main part, and a timing chart of signal waveforms at each point in the circuit diagram, respectively, of the embodiment according to the invention set forth in claim (2). 3...Light emitter circuit, 4...Light receiving circuit, 8...Signal processing circuit, 13-17...JK flip-flop, 20-22, 24-26...AND circuit, 19
...AND circuit (set output AND means), 23
...AND circuit (reset output logical product means).

Claims (1)

【実用新案登録請求の範囲】 (1) パルス変調された光を投光する投光回路お
よび投光回路からの光を受光する受光回路と、 受光回路のパルス信号が入力されるn段のシフ
トレジスタと、m段目(1≦m<n)およびn段
目のシフトレジスタのセツト出力の論理積をm+
1段目以降のシフトレジスタの直接セツト端子に
入力するセツト出力論理積手段と、m段目および
n段目のシフトレジスタのリセツト出力の論理積
をm+1段目以降のシフトレジスタの直接リセツ
ト端子に入力するリセツト出力論理積手段と、を
有する信号処理回路と、 から構成したことを特徴とする光電スイツチ回路
。 (2) 前記投光回路に供給するパルス信号を発生
する第1の発振器と、前記シフトレジスタの各段
に入力するクロツクパルスを発生する第2の発振
器と、を設けた請求項(1)に記載の光電スイツチ
回路。
[Scope of Claim for Utility Model Registration] (1) A light emitter circuit that emits pulse-modulated light, a light receiver circuit that receives light from the light emitter circuit, and an n-stage shift to which the pulse signal of the light receiver circuit is input. The logical product of the register, the set output of the m-th stage (1≦m<n) and the n-th stage shift register is m+
The set output logical product means inputs to the direct set terminals of the shift registers from the first stage onward, and the logical product of the reset outputs of the m-th and n-th stage shift registers is inputted to the direct reset terminals of the shift registers from the m+1st stage onward. 1. A photoelectric switch circuit comprising: a signal processing circuit having reset output AND input means; (2) According to claim (1), further comprising a first oscillator that generates a pulse signal to be supplied to the light projection circuit, and a second oscillator that generates a clock pulse that is input to each stage of the shift register. photoelectric switch circuit.
JP1990049440U 1990-05-11 1990-05-11 Photoelectric switch circuit Expired - Lifetime JPH0749428Y2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP1990049440U JPH0749428Y2 (en) 1990-05-11 1990-05-11 Photoelectric switch circuit
DE69125522T DE69125522T2 (en) 1990-05-11 1991-05-08 Photoelectric circuit
EP96114375A EP0753939A1 (en) 1990-05-11 1991-05-08 Photoelectrical switching circuit
EP91304150A EP0456482B1 (en) 1990-05-11 1991-05-08 Photoelectrical switching circuit
US07/697,894 US5099113A (en) 1990-05-11 1991-05-08 Photoelectrical switching circuit with frequency divider circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990049440U JPH0749428Y2 (en) 1990-05-11 1990-05-11 Photoelectric switch circuit

Publications (2)

Publication Number Publication Date
JPH048984U true JPH048984U (en) 1992-01-27
JPH0749428Y2 JPH0749428Y2 (en) 1995-11-13

Family

ID=31567134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990049440U Expired - Lifetime JPH0749428Y2 (en) 1990-05-11 1990-05-11 Photoelectric switch circuit

Country Status (1)

Country Link
JP (1) JPH0749428Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139776A (en) * 1984-12-11 1986-06-27 Riide Denki Kk Photoelectric switch

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139776A (en) * 1984-12-11 1986-06-27 Riide Denki Kk Photoelectric switch

Also Published As

Publication number Publication date
JPH0749428Y2 (en) 1995-11-13

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