JPH0480134U - - Google Patents
Info
- Publication number
- JPH0480134U JPH0480134U JP12247890U JP12247890U JPH0480134U JP H0480134 U JPH0480134 U JP H0480134U JP 12247890 U JP12247890 U JP 12247890U JP 12247890 U JP12247890 U JP 12247890U JP H0480134 U JPH0480134 U JP H0480134U
- Authority
- JP
- Japan
- Prior art keywords
- count
- counter
- clock signal
- change
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 claims 2
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は、本考案の１実施例としてのアツプダ
ウンカウンタのキヤリ信号出力部の構成を示す回
路図、第２図ａ，ｂは、第１図の回路の動作を説
明するタイミング図、第３図は、従来技術におけ
るアツプダウンカウンタのキヤリ信号出力部の１
例を示す回路図、第４図は、第３図の回路の動作
を説明するタイミング図、第５図は、この種のア
ツプダウンカウンタの概略構成を例示する図であ
る。
符号の説明、１，２，３，４……アンドゲート
、５……オアゲート、６……Ｄフリツプフロツプ
、７，８１，８２，８３，８４……インバータ、
１１，１２，１３，１４……アンドゲート、１５
……オアゲート、１６……インバータ、Ｃ１，Ｃ
２……カウンタ、Ｄ／……アツプ／ダウン信号
、ＣＬＫ……クロツク信号。
1 is a circuit diagram showing the configuration of a carry signal output section of an up-down counter as an embodiment of the present invention; FIGS. 2a and 2b are timing diagrams illustrating the operation of the circuit in FIG. 1; Figure 3 shows one of the carry signal output parts of the up-down counter in the prior art.
FIG. 4 is a timing diagram illustrating the operation of the circuit of FIG. 3, and FIG. 5 is a diagram illustrating a schematic configuration of this type of up-down counter. Explanation of symbols, 1, 2, 3, 4...AND gate, 5...OR gate, 6...D flip-flop, 7, 81, 82, 83, 84...inverter,
11, 12, 13, 14...and gate, 15
...OR gate, 16...Inverter, C1, C
2... Counter, D/... Up/down signal, CLK... Clock signal.
Claims (1)
トダウンして０から９までのカウント数を出力す
る第１のカウンタと、該第１のカウンタから出力
されるキヤリ信号を順次カウントアツプ又はカウ
ンドダウンしてその上位の桁の０から９までのカ
ウント数を出力する第２のカウンタとをそなえた
アツプダウンカウンタであつて、 カウントアツプ動作からカウントダウン動作へ
の変化時点およびカウントダウン動作からカウン
トアツプ動作への変化時点を該クロツク信号の立
上り時点に同期させる手段と、カウントアツプ動
作時には該第１のカウンタの出力が０となつたと
きに該クロツク信号と同期したキヤリ信号を出力
する手段と、カウントダウン動作時には該第１の
カウンタの出力が９となつたときに該クロツク信
号と同期したキヤリ信号を出力する手段とをそな
えることを特徴とするアツプダウンカウンタ。[Claims for Utility Model Registration] A first counter that sequentially counts up or down a clock signal and outputs a count number from 0 to 9; An up-down counter that is equipped with a second counter that counts down and outputs the count number from 0 to 9 of the upper digits, the time point of change from count-up operation to count-down operation, and the time of change from count-up operation to count-up operation. means for synchronizing the time of change to the clock signal with the rising edge of the clock signal; means for outputting a carry signal synchronized with the clock signal when the output of the first counter becomes 0 during a count-up operation; An up-down counter comprising means for outputting a carry signal synchronized with the clock signal when the output of the first counter reaches 9 during operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12247890U JP2539681Y2 (en) | 1990-11-26 | 1990-11-26 | Up / down counter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12247890U JP2539681Y2 (en) | 1990-11-26 | 1990-11-26 | Up / down counter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0480134U true JPH0480134U (en) | 1992-07-13 |
| JP2539681Y2 JP2539681Y2 (en) | 1997-06-25 |
Family
ID=31870257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12247890U Expired - Lifetime JP2539681Y2 (en) | 1990-11-26 | 1990-11-26 | Up / down counter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2539681Y2 (en) |
-
1990
- 1990-11-26 JP JP12247890U patent/JP2539681Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2539681Y2 (en) | 1997-06-25 |
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