JPH03125532U - - Google Patents

Info

Publication number
JPH03125532U
JPH03125532U JP3387990U JP3387990U JPH03125532U JP H03125532 U JPH03125532 U JP H03125532U JP 3387990 U JP3387990 U JP 3387990U JP 3387990 U JP3387990 U JP 3387990U JP H03125532 U JPH03125532 U JP H03125532U
Authority
JP
Japan
Prior art keywords
clock pulses
counter
shift register
stage shift
pulses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3387990U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3387990U priority Critical patent/JPH03125532U/ja
Publication of JPH03125532U publication Critical patent/JPH03125532U/ja
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す回路図、第2
図は一実施例の動作を説明するタイミング図、第
3図は一実施例の回路のプリセツト値と分周比の
関係を示す図、第4図、第5図および第6図は本
考案の他の実施例を示す回路図である。第7図は
および第8図は従来回路を示す図である。 1……カウンタ、5……フリツプフロツプ、6
……ノア回路。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a timing diagram explaining the operation of one embodiment, FIG. 3 is a diagram showing the relationship between preset values and frequency division ratios of the circuit of one embodiment, and FIGS. 4, 5, and 6 are diagrams of the circuit of the present invention. FIG. 7 is a circuit diagram showing another embodiment. FIGS. 7 and 8 are diagrams showing conventional circuits. 1...Counter, 5...Flip-flop, 6
...Noah circuit.

Claims (1)

【実用新案登録請求の範囲】 クロツクパルスの計数を行ない、N個のクロツ
クパルスに対して1個のキヤリパルスを出力する
カウンタと、 前記カウンタからのキヤリパルスを前記クロツ
クパルスに同期して記憶するM段シフトレジスタ
と、 前記M段シフトレジスタの記憶出力により、前
記カウンタの計数動作を前記クロツクパルスM個
分遅延させる計数遅延回路とを備えたことを特徴
とする分周回路。
[Claims for Utility Model Registration] A counter that counts clock pulses and outputs one carry pulse for every N clock pulses, and an M-stage shift register that stores the carry pulses from the counter in synchronization with the clock pulses. and a counting delay circuit that delays the counting operation of the counter by the number of the M clock pulses based on the storage output of the M-stage shift register.
JP3387990U 1990-03-30 1990-03-30 Pending JPH03125532U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3387990U JPH03125532U (en) 1990-03-30 1990-03-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3387990U JPH03125532U (en) 1990-03-30 1990-03-30

Publications (1)

Publication Number Publication Date
JPH03125532U true JPH03125532U (en) 1991-12-18

Family

ID=31537881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3387990U Pending JPH03125532U (en) 1990-03-30 1990-03-30

Country Status (1)

Country Link
JP (1) JPH03125532U (en)

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