JPH0478184B2 - - Google Patents

Info

Publication number
JPH0478184B2
JPH0478184B2 JP59243306A JP24330684A JPH0478184B2 JP H0478184 B2 JPH0478184 B2 JP H0478184B2 JP 59243306 A JP59243306 A JP 59243306A JP 24330684 A JP24330684 A JP 24330684A JP H0478184 B2 JPH0478184 B2 JP H0478184B2
Authority
JP
Japan
Prior art keywords
package
welding
layer
pins
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59243306A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61123160A (ja
Inventor
Shigeki Harada
Kyoshi Muratake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59243306A priority Critical patent/JPS61123160A/ja
Publication of JPS61123160A publication Critical patent/JPS61123160A/ja
Publication of JPH0478184B2 publication Critical patent/JPH0478184B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP59243306A 1984-11-20 1984-11-20 半導体装置パツケ−ジのピン溶接法 Granted JPS61123160A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59243306A JPS61123160A (ja) 1984-11-20 1984-11-20 半導体装置パツケ−ジのピン溶接法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59243306A JPS61123160A (ja) 1984-11-20 1984-11-20 半導体装置パツケ−ジのピン溶接法

Publications (2)

Publication Number Publication Date
JPS61123160A JPS61123160A (ja) 1986-06-11
JPH0478184B2 true JPH0478184B2 (https=) 1992-12-10

Family

ID=17101869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59243306A Granted JPS61123160A (ja) 1984-11-20 1984-11-20 半導体装置パツケ−ジのピン溶接法

Country Status (1)

Country Link
JP (1) JPS61123160A (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4970570A (en) * 1986-10-28 1990-11-13 International Business Machines Corporation Use of tapered head pin design to improve the stress distribution in the braze joint

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5466467A (en) * 1977-11-04 1979-05-29 Hitachi Ltd Method of connecting parts to printed circuit substrate

Also Published As

Publication number Publication date
JPS61123160A (ja) 1986-06-11

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