JPH0478011B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuit devices, and more particularly to the interconnection of high-density complementary symmetric metal oxide semiconductor (hereinafter referred to as CMOS) devices manufactured using silicon-on-sapphire (hereinafter referred to as SOS) technology. Regarding the formation method.

To increase the packing density of devices in integrated circuits, 2
There is a need to reduce the space required for interconnection between one or more devices. Connecting two diffusion regions, traditionally separated by an intermediate gate line, requires the use of bulky metal jumpers or the use of doped epitaxial layers that bypass the gate line, taking up considerable space. It was hot.

In self-aligned silicon gate CMOS technology,
between two diffusion regions with a conductive line spanning them.
MOS operation may occur, and depending on the conductivity type of the diffusion region and the type of conductive line thereon, the diffusion region may or may not be connected in MOS operation. Doped polysilicon gate lines are generally used in high density regions.

In order to reliably connect two diffusion regions separated by a doped polycrystalline silicon line with a low resistance ohmic circuit, an extra diffusion may be performed before depositing the polycrystalline silicon line. , such a circuit has nothing to do with MOS operation. This extra diffusion region underlies the polycrystalline silicon line and has the same conductivity type as the interconnected diffusion regions. Since P+ type and N+ type diffusions are used in CMOS integrated circuits, it is necessary to add a total of two mask operations, one for N+ diffusion and one for P+ diffusion.

The present invention provides a unique method of forming a "universal interconnect" that is used to connect between P+ or N+ diffusion regions and requires only one additional mask operation. A detailed description will be given below with reference to the accompanying drawings.

FIG. 1 shows a portion of an integrated circuit structure 10 formed by conventional methods. This integrated circuit structure 10 includes an insulating substrate 1
2 and the semiconductor island portion 14, 1 formed thereon.
6. Generally, the insulating substrate 12 is made of sapphire and the semiconductor islands 14, 16 are made of silicon in the well-known SOS technique. As shown, the island 14 includes a pair of P+ type diffusion regions 18, 20 separated by a P type region 22, and the island 14 is covered with a silicon dioxide layer 24, and the silicon dioxide layer 24 is covered with a silicon dioxide layer 24. A P+ type doped polycrystalline silicon line 26 is mounted on the line 24. P-type region 22
The purpose of is to provide a conductive path between P+ type regions 18,20.

Similarly, the silicon island 16 includes a pair of N+ type regions with an N type region sandwiched between them.
6 is covered with a silicon dioxide layer 34, and an N+ type polycrystalline silicon line 36 is placed on the silicon dioxide layer 34. The purpose of the N-type region 32 is N+
The purpose is to provide a reliable conductive path between mold regions 28 and 30.

Typically, this integrated circuit 10 has P+ type regions 18, 20.
The polycrystalline silicon line 26 is manufactured by a self-alignment method in which the polycrystalline silicon line 26 is doped to P+ type by ion implantation. At the same time, N+ polysilicon line 36 is also doped with the same ion implantation process that dopes regions 28 and 30 N+. Therefore, it was necessary to dope the P-type region 22 and the N-type region 32 in separate processes requiring separate photomasks.

It is extremely desirable to eliminate the photomask process, since the yield of a semiconductor manufacturing process decreases as the number of process steps increases. Therefore, the present invention is desirable in that it eliminates at least one photomask process in the production of the "universal crossover connection" which is the gist of the invention.

FIG. 2 shows a portion of a semiconductor integrated circuit 100 manufactured using the method of the present invention. Integrated circuit structure 100 includes an insulating substrate 38 and single crystal semiconductor islands 40 and 42 formed thereon. In the preferred embodiment of the invention, insulating substrate 38 is comprised of sapphire and semiconductor islands 40 and 42 are comprised of silicon. The semiconductor island region 40 has a pair of P+
It includes mold regions 44, 46 and a general purpose crossover 48 therebetween and is covered by a silicon dioxide layer 50.
A P+ type impurity-doped polycrystalline silicon line 52 is provided on the silicon dioxide layer 50 on the general-purpose crossover connection 48. Similarly, the semiconductor island region 42 includes a pair of N+ type regions 54 and 56 and a general-purpose crossover connection 58 therebetween, and is covered with a silicon dioxide layer 60 , and the silicon dioxide layer 60 on the general-purpose transition connection 58 is covered with a silicon dioxide layer 60 . An N+ type impurity-doped polycrystalline silicon line 62 is provided above.

The general-purpose crossover connections 48 and 58 are each connected to the P-type area 6.
6 and an N-type region 64 thereon, thus P
A conductive path is formed between the + type regions 44 and 46 via the P type lower layer portion 66 of the general-purpose crossover connection 48. Similarly, a conductive path is formed between the N+ type regions 54 and 56 via the N type upper layer portion 64 of the general-purpose crossover connection 58. Therefore, the general purpose crossover connections 48, 58 are "universal" in that they can be used to connect two N+ type regions or two P+ type regions.

General-purpose crossover connection 48, 5 of the recommended embodiment of this invention
In the formation method No. 8, approximately equal amounts of a slow-diffusing N-type impurity (dopant) and a fast-diffusing P-type impurity (dopant) are ion-implanted through the opening of a common mask, and then these impurities (dopants) are ) is diffused to separate the N-type layer 64 and the P-type layer 66 parallel to the surface of the substrate 38 due to the difference in diffusion speed between the two.

As a typical example, arsenic is used as an N-type dopant, boron is used as a P-type dopant, and both dopants are added to the oxide layers 50 and 6.
The ions are implanted through 0 to a concentration of approximately 2×10 ¹⁴ atoms/cm ² . This doping results in an ohmic conductor with a sufficiently low sheet resistance that it is virtually irrelevant to MOS operation. The maximum sheet resistance for making the conductor ohmic and essentially independent of MOS operation is believed to be about 1000 Ω/square, corresponding to an impurity concentration of about 10 ¹⁸ atoms/cm ³ . Epitaxial silicon island region 4
The thickness of 0.42 is generally about 6000 Å. The remaining steps after ion implantation in the manufacturing process of the integrated circuit 100 are equivalent to 50-minute diffusion at 1050° C. As a result of this diffusion, an N-type region 64 is formed on the P-type region 66, and a general-purpose crossover connection is formed. 48, 58 are formed.

The conductivity of the P-type and N-type electrical paths of the general-purpose crossover connections 48 and 58 is P as in the regions 22 and 32 in FIG.
Although lower than that obtained by separate diffusion treatments for type and N type, this general purpose crossover is still sufficient as a conductive path.

Although the above-described embodiments of the invention were carried out by implanting equal amounts of boron and arsenic, the relative amounts of boron and arsenic can be varied appropriately so that the conductivity efficiency of both conductive paths is approximately 40%. Here, the N-type arsenic implanted circuit 64 of the general-purpose crossover connection 58 is
The efficiency was approximately 55% of that of a single N-type region, such as region 32 in FIG. Similarly, P of crossover connection 48
The efficiency of the boron-type implanted path 66 was about 33% of that of the single P-type region 22 of FIG.

3 and 4 show the results of ion implantation of boron and arsenic at an implantation energy of about 150 KeV to a total amount of 2×10 ¹⁴ atoms/cm ² of each impurity, followed by diffusion at 1050° C. for 50 minutes. FIG. 3 shows the physical appearance of a general purpose crossover connection 70 during device manufacture. The crossover connection 70 connects boron and arsenic (indicated by arrows in FIG. 3) through a silicon dioxide layer 72 with a thickness of approximately 1000 Å.
It is formed by ion implantation using a mask of shaped photoresist layer 74 having openings. The openings are located just above the gaps between P+ regions 44 and 46 and between N+ regions 54 and 56. At this point in the process, no drain or source has yet formed.

After diffusion of the implanted ions, the interconnect 70 reaches the sapphire substrate 80 through a relatively shallow N-type layer 76 and, if no drain and source are formed (as shown in FIG. 2), an N-type layer 82. lower layer P
It has a mold layer 78. As a result of diffusion, P-type boron ions diffuse into a deeper and wider area than N-type arsenic ions, but in reality, the regions on both sides where the crossover connection 70 connects are doped with N+ type or P+ type, and the structure after diffusion is The N-type region 76 is formed as shown in FIG.
is not isolated from adjacent regions by P-type region 78.

FIG. 4 graphically illustrates the results of ion diffusion during the formation of the general purpose crossover connection 70 of FIG. Specifically, the concentration of arsenic ions is substantially higher than that of boron near the surface of the epitaxial silicon layer, but at a concentration of about 2000 Å.
At the depth of , the boron concentration exceeds the arsenic concentration and remains higher than the arsenic concentration up to the sapphire substrate surface.

According to the experimental results, the resistance value of the crossover connection with a width of about 10μ matched well with the calculated value. To be more specific, the calculated value is 600Ω/square for the measured sheet resistance of the N-type circuit
780Ω/square, P-type circuit resistance measurement value approximately 200Ω/
The calculated value for a square was 220Ω/square.

It should be noted that the practicality of the general purpose crossover connections described above is greatest when the semiconductor body is mounted on an insulating substrate. This general-purpose crossover connection can therefore also be used in an all-silicon case, ie, when one of the diffusion regions to be connected is at power supply potential, but SOS type CMOS technology is the most suitable application.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a part of a conventional integrated circuit structure which does not include a general-purpose crossover connection formed by the method of the present invention, and FIG. 2 shows an SOS type CMOS structure including a general-purpose crossover connection formed by the method of the present invention. Some cross-sectional views,
FIG. 3 is a cross-sectional view of a portion of an integrated circuit structure for explaining the method of the present invention, and FIG. 4 is a diagram showing calculated concentration gradients of boron and arsenic for the type used in the present invention. 40, 42... single crystal semiconductor layer, 44-46,
54-56...Pair of areas, 48, 58...Part between the pair of areas (general-purpose crossover connection), 64...Second
layer, 66... first layer, 50, 60... insulating layer.

Claims (1)

[Scope of Claims] 1. A substrate made of an insulating material and at least two island-like regions made of a single-crystal semiconductor material layer formed on the substrate, each of the island-like regions having the same conductivity type. a pair of mutually separated individual regions, and both individual regions in one island-like region have one conductivity type, and both individual regions in the other island-like region have the opposite conductivity type. A method for forming a connection between said discrete regions of an integrated circuit having: forming a mask layer over a surface of said semiconductor material layer; forming an opening in a portion corresponding to the gap between the two individual regions; and adding two different impurities, one of which has one conductivity type and the other of which has the opposite conductivity type. Injecting into the semiconductor layer through an opening formed in the mask layer, and simultaneously forming a conductive layer consisting of upper and lower layers of different conductivity types between both individual regions in the at least two island-like regions. process and
A method for forming a crossover connection for an integrated circuit, the method comprising: 2. The crossover connection forming method according to claim 1, wherein one of the two impurities is a slow-diffusing impurity and the other is a fast-diffusing impurity. 3. The crossover connection forming method according to claim 1 or 2, wherein the two impurities are implanted by ion implantation. 4. The method for forming a crossover connection according to claim 2, wherein the fast-diffusing impurity is boron and the slow-diffusing impurity is arsenic.