FR2463977A1 - CROSSING BELOW FOR INTEGRATED CMOS / SOS CIRCUITS WITH HIGH DENSITY - Google Patents

Abstract

THE PRESENT INVENTION CONCERNS COMPONENTS OF INTEGRATED CMOSSOS CIRCUITS AND MORE PARTICULARLY A CROSSING FROM BELOW FOR SUCH CIRCUITS. THE CROSSING FROM BELOW 48 IS CHARACTERIZED BY THE SUPERPOSITION OF TWO LAYERS 64 AND 66 OF OPPOSED CONDUCTIVITY. SUCH A CROSSING FROM BELOW REQUIRES ONLY A SIMPLE ADDITIONAL MASKING STAGE.

Description

The present invention relates to integrated circuit components.

  In particular, the invention relates to complementary metal oxide semiconductor (CMOS) components having a high density symmetry, particularly those manufactured in the

silicon technology on sapphire.

  In order to increase the integration density of the components in an integrated circuit, it is preferable to eliminate the space required for interconnections between two or more components. So far, it has been necessary to use bulky metal bridges - on the surface in order to interconnect diffusions

  which leaves separated by a series of interposition doors.

  Alternatively, doped epitaxial layers that bypass the series of gates, thus

  consuming a large area, were also used.

  In CMOS processes with self-aligned silicon gate, the action of the metal oxide semiconductor can occur between two diffusions which have a conductive line superimposing them. Depending on the type of conductivity of the diffusions, and the type of conductive line superimposing them, broadcasts can

  or can not be connected by the semi-action

  metal oxide conductor. Typically, doped polycrystalline silicon gate lines are

  used in high density regions.

  In order to selectively connect two diffusions which are separated by a doped polycrystalline silicon line with a low ohmic resistance path, additional diffusion can be made in priority of the deposition of the polycrystalline silicon line. Such a path would be independent of the action. metal oxide semiconductor. The additional diffusion, which is located under the polycrystalline silicon line, is of the same type of conductivity as the diffusions it connects. together. Because of P + and N + broadcasts

  are both used in semi-integrated circuits

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  complementary metal oxide conductors, two additional masking stages, for example one for diffusions

  N + and one for P + broadcasts are required.

  The present invention is a method and a structure for providing a single "universal crossover" that can be used to connect together either P + or N + broadcasts and that requires only a masking stage.

additional simple.

  Other features and advantages of the invention

  will appear better in the following detailed description

  and refers. in the accompanying drawings, and in which: - Figure 1 is a cross-sectional view of a portion of the structure of an integrated circuit of the prior art which does not contain the structure of the universal under cross of the present invention ; FIG. 2 is a cross-sectional view of a CMOS / SOS structure that includes the universal under crossover of the present invention; FIG. 3 is a cross-sectional view of a structure of an integrated circuit showing the fabrication method of the present invention; and FIG. 4 is a profile graph calculated for arsenic and boron doses of the type used in FIG.

present invention.

  Referring now to FIG. 1, a portion of a structure 10 of the prior art integrated circuit is shown. The structure 10 of the integrated circuit comprises

  an insulating substrate 12 on which semi-conductor islands

  14, 16 have been formed. In general, the substrate

  insulation 12 is composed of sapphire and the semi-islands

  Conductors 14, 16 are composed of silicon in the known SOS technology. The island 14 is shown by enclosing a pair of P + diffusions 18, 20 which are separated by a P-type region 22. A silicon dioxide layer 24 overcomes the island 14 and a P + doped polycrystalline silicon line 26 overcomes the silicon dioxide layer 24. The purpose of the P-type region is

  provide a conductive path between the P + regions 18, 20.

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  In a similar manner, the silicon island 16 comprises a pair of separate regions 28, 30 N + having between them a region 32 of the N type. A layer of silicon dioxide

  34 overcomes island 16 and a polycrystalline silicon line

  N + type flax 36 overcomes the silicon dioxide layer 34. The purpose of the N-type region 32 is to

  provide a conductive path between N + regions 28, 30.

  Characteristically, the integrated circuit 10 is fabricated using a self-aligned technique in which the polycrystalline silicon line 26 is doped to the P + type conductivity by ion implantation at the same time as the P + region 18 and 20 are doped with a conductivity P +. Similarly, the N + doped polycrystalline silicon line 36 is doped in the same ion implantation step which doped the regions 28, 30 with the N + conductivity. Nevertheless, it was necessary to boost the P-type region 22 and the N-type region 32

  in separate steps that each require photo-

separate masks.

  In view of the fact that the efficiency in a semiconductor manufacturing process decreases as the number of manufacturing steps increases, the removal of a photomask step is highly desirable. Accordingly, the present invention is desirable in that it

  eliminates at least one photomask step in the manufacture

  of the "universal under crossing" which is the object

of the present invention.

  Referring now to Figure 2, a portion of the integrated circuit of a semiconductor 100 employing the present invention is shown. The structure of the integrated circuit 100 comprises an insulating substrate 38 on which are formed single-crystal semiconductor islands, 42. In the preferred embodiment of the invention, the insulating substrate 38 is composed of sapphire and the semiconductor wires 40 , 42 are composed of silicon. The semiconductor island 40 comprises a pair of P + regions 44,

  46 with a universal bottom path 48 between them.

  A layer of silicon dioxide 50 overcomes the 42.

  A P + doped polycrystalline silicon line 52 overcomes the silicon dioxide layer 50 above the universal under cross-over 48. Similarly, the semiconductor wire 42 includes a pair of N + regions 54, 56 having 58. A layer of silicon dioxide 60 overcomes the island 42 and an N + doped polycrystalline silicon line 60 overcomes the silicon dioxide layer 60 overhead.

  of the universal under cross 58.

  The universal below crossings 48, 58 each comprise an N-type region 64 which overcomes a P-type region 66. As a result, a conductive path is created between the P + regions 44 and 46 across the lowest part of the P-type. 64 of the universal undercut 48. Similarly, a conductive path between the N + regions 54, 56 is created through the top of the N 66 type of the universal under cross 58. The universal under crossings 48, 58 are, accordingly,

  universal in that they can be used to connect

  ter two N + regions or two P + regions .-

  In order to construct the universal below crossings 66 of the preferred embodiment of the present invention, a slow N-type diffusing dopant and a fast

  P-type diffusing dopants are both implanted appro-

  approximately at the same total dose through a common opening mask. Following the ion implantation, the dopants are scattered, and they are separated into N-type and P-layer 64, which are parallel to the surface of the substrate.

  dice to their differentdifferent diffusion.

  In a typical example, arsenic is used as N-type dopant and boron is used as a P-type dopant. The dopants are implanted both at a dose of about 2 X 10 14 atoms / cm 2 through the oxide layers 50, 60. This doping will result in an ohmic conductor having a resistance per unit

  square surface sufficiently low to be effective-

  independent of the semiconductor metal oxide action.

  Resistance per square unit less than

  1000 ohms / square, corresponding to a concentration of impu-

  The value of about 1018 atoms / cm 3 is considered to be the maximum resistance per square unit of area that is useful for making an ohmic conductor and effectively independent of the metal oxide semiconductor action.

  Silicon epitaxial islands 40, 42 in a typical manner

  The ionization implantation, the steps remaining in the fabrication of the integrated circuit 100 are equivalent to a diffusion of 50 minutes at 10500C. The effect of this diffusion is the creation of the N 64 region above the P 66 region to create the universal under crossover

48, 58.

  While the conductivity of the P + and N + paths in the crossings below 48, 58 is less than that which could be obtained from isolated scattering of the P and N type, such as the regions 22, 32 of FIG. suitably conductives are

  provided by the universal under crossings 48, 58.

  While the invention has been practiced with equal implantation dosages for boron and arsenic, the relative boron and arsenic implantation assays can be optimized so that there is conductivity of approximately 40% for each path. With equal implantation assays up to the point of use, the yield of the N64-type arsenic implantation path of the universal crossover 58 was approximately 55% of that of a single N-type region, such as region 32 of Figure 1. Similarly, the P-boron implantation 66 of the crossover 48 had a yield of about 33% of the yield.

  of the simple P-type region 22 of FIG.

  Referring now to Figures 3 and 4, boron and arsenic union effects implanted at implantation energies of approximately 150 KeV at total dosages of 2 X 10 14 atoms / cm 2 of each dopant followed by a 50 minute diffusion at 10500C is indicated. In Figure 3, the physical appearance of a universal under crossover 70 during manufacture of a component is indicated. The cross-over 70 is formed by the implantation of boron ion and arsenic (as indicated by the arrows in Figure 3) through a layer of silicon dioxide 72 having a thickness of about o 1000 A. The implantation ion is masked by a defined photoresistor layer 74. At this manufacturing step

  drains and springs have not yet been formed.

  Depending on the diffusion of the implanted ions, the undercut 70 would have a N-type layer 76 which is relatively shallow and a P-layer 78 below which extends over the sapphire 80 substrates in the N-layer. if no drains or sources (as shown in Figure 2) were provided. As a result of diffusion, the P-type boron ions tend to diffuse both more deeply and over a larger area than the arsenic ions of the type N. In

  current practice the regions of each clergy of the cross-

  70, that the crossover below 70 is intended to interconnect, would be doped with either a conductivity N + or a conductivity P + and the resulting structure, after diffusion, would look like the urn of the structures shown in Figure 2, by example the N 76 region would not be isolated by the P region 78

adjacent regions.

  Referring now to FIG. 4, the ion diffusion results for formation of the universal under crossover 70 of FIG. 3 are shown graphically. In particular, the concentration of arsenic ions is substantially greater than the concentration of boron ions near the surface of the

  silicone epitaxial layer. Similarly, the concentration

  Boron ion concentration exceeds the concentration of arsenic ions to a depth of approximately 2000 A, and remains higher than the concentration of ions.

  arsenic on the surface of the sapphire substrate.

  The experimental results obtained by the inventor compare well the resistance values calculated for a bottom crossing having a width of about microns. In particular, the N-type path has a measured resistivity of 600 ohms / square compared to a calculated resistivity of 780 ohms / square, and the P-type path has a measured resistivity of about 200 ohms / square.

  compared to a calculated resistivity of 220 ohms / square.

  It should be noted that the utility of the below-universal crossovers described here is greater in applications in which a semiconductor body

  overcomes an insulating substrate. As a result, the technology

  CMOS / SOS is a perfect application for cross-

  although it can be used in silicon block processes, for example where one of the broadcasts to be connected is

  power supply potential.

  Of course, the invention is not limited to. embodiment described and shown which has been given by way of example. In particular, it includes all means constituting technical equivalents

  described means, as well as their combinations, if these

  These are executed according to his spirit and implemented

  as part of the protection as claimed.

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R E V E N D I A T IONS

  An improved undercut crossing for integrated circuit components comprising a single crystal semiconductor material layer; a pair of spaced regions of the same conductivity type formed in the layer of said semiconductor; and a portion of the layer of said semiconductor being between said region of said regions, characterized in that said portion (48) of said semiconductor layer is composed of a first layer (66) a conductivity type and a second layer (64) surmounting said first layer, said second layer being opposite in the conductivity type to said first layer, by means of which

  one of said layers of said portion connects ohmically

  together said pairs of spaced regions,

regardless of the MOS action.

  An improved undercut crossing according to claim 1, characterized in that said first layer (66) is of the P-type and said second layer (64) is of the N-type. 3. An improved undercut crossing according to claim 2, characterized in that the first layer

  (66) is doped with a fast diffusion type P dopant.

  4. improved under crossover according to claim 3, characterized in that said dopant

P type is boron.

  5. Advanced undercut crossing according to claim 2, characterized in that the second layer

  (64) is doped with a slow diffusion N-type dopant.

  6. Advanced under crossing according to claim 5, characterized in that said dopant of the

N type is arsenic.

  An improved method of forming a bottom crossing for integrated circuits fabricated in single crystalline layers comprising the step of forming a pair of spaced regions of the same conductivity type in a single crystal semiconductor layer; characterized in that a masking layer (74) is formed above the semiconductor layer (82); openings are defined in said masking layer above the gap between said spaced regions; two different impurities are introduced into said semiconductor layer, one of said impurities being of one type of conductivity and the other of said impurities

  being of a type of opposite conductivity.

  8. Process according to claim 7, characterized in that one of the abovementioned impurities is a slow diffusion impurity and the other of said impurities is

a fast diffusion impurity.

  9. Process according to claim 8, characterized in that the abovementioned impurities are introduced by

ion implantation.

  10. Process according to claim 8, characterized in that the rapid diffusion impurity is boron and

  the slow diffusion impurity is arsenic. -