GB2056771A - Crossunders for high density CMOS/SOS integrated circuits - Google Patents
Crossunders for high density CMOS/SOS integrated circuits Download PDFInfo
- Publication number
- GB2056771A GB2056771A GB8025630A GB8025630A GB2056771A GB 2056771 A GB2056771 A GB 2056771A GB 8025630 A GB8025630 A GB 8025630A GB 8025630 A GB8025630 A GB 8025630A GB 2056771 A GB2056771 A GB 2056771A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- crossunder
- improved
- type
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 13
- 229910052796 boron Inorganic materials 0.000 claims description 12
- 239000002019 doping agent Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 6
- 239000010980 sapphire Substances 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- -1 boron ions Chemical class 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 4
- 239000007943 implant Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A structure for a "universal crossunder" (48/58) which can reliably interconnect two spaced regions (44,46/54,56) of semiconductor material of the same conductivity type is described. The structure is comprised of two layers, one P type and the other N type which lies in the area between the regions which are to be electrically joined. Accordingly, whether the regions to be electrically connected are P type or N type, electrical connection is made between them through one of the layers of the crossunder. The method of making the "universal crossunder" entails, simultaneously introducing a fast diffusing impurity of one conductivity type and a slow diffusing impurity of the opposite conductivity type into the area between the regions to be joined. Thus, electrical contact between the two spaced regions will be made through one or the other of the layers of the circuit. <IMAGE>
Description
SPECIFICATION
Crossunders for high density CMOS/SOS integrated circuits
The present invention relates to integrated circuit devices. In particular, the invention relates to high density complementary symmetry metal oxide semiconductor (CMOS) devices, particularly those manufactured in the silicon-on-sapphire (SOS) technology.
In order to increase the packing density of devices in an integrated circuit, it is desirable to decrease the space required for interconnects between two or more devices. Heretofore, it has been necessary to utilize area consuming metal jumpers in order to interconnect two diffusions which are separated by an intervening gate line. Alternatively, doped epitaxial layers which run around the gate lines, thereby consuming considerable area, have also been used.
In self-aligned silicon gate CMOS processes,
MOS action can occur between two diffusions which have a conductive line lying over them.
Depending upon the conductivity type of the diffusions, and upon the type of conductive line overlying them, the diffusions may or may not be connected by MOS action. Typically, doped polycrystalline silicon gate lines are used in high density regions.
In order to reliably connect two diffusions which are separated by a doped polycrystalline silicon line with a low resistance ohmic path, an extra diffusion can be made prior to the deposition of the polycrystalline silicon line. Such a path would be independent of
MOS action. The extra diffusion, which is located under the polycrystalline silicon line, is of the same conductivity type as the diffusions which it connects together. Since both
P + and N + diffusions are used in CMOS integrated circuits, two additional masking steps, i.e. one for N + diffusions and one for
P + diffusions, are required.
The present invention is a method and structure for providing a unique "universal crossunder" which may be used to connect either P + or N + diffusions together and which requires only a single additional masking step.
In the Drawings:
Figure 1 is a cross-sectional view of a portion of an integrated circuit structure of the prior art which does not include the universal crossunder structure of the present invention;
Figure 2 is a cross-sectional view of a
CMOS/SOS structure which includes the universal crossunder of the present invention;
Figure 3 is a cross-sectional view of a portion of an integrated circuit structure showing the method of manufacturing the present invention; and
Figure 4 is a graph of the calculated profiles for boron and arsenic doses of the type used in the present invention.
Referring now to Fig. 1, a portion of an integrated circuit structure 10 of the prior art is shown. The integrated circuit structure 10 includes an insulating substrate 12 upon which semiconductor islands 14, 16 have been formed. Generally, the insulating substrate 12 is comprised of sapphire and the semiconductor islands 14, 16 are comprised of silicon in the well-known SOS technology.
The island 14 is shown to include a pair of
P + diffusions 18, 20 which are separated by a P type region 22. A silicon dioxide layer 24 overlies the island 14 and a P + doped polycrystalline silicon line 26 overlies the silicon dioxide layer 24. The purpose of the P type region is to provide a conductive path between the P + regions 18, 20.
Similarly, the silicon island 16 comprises a pair of separated N + regions 28, 30 having an N type region 32 lying therebetween. A silicon dioxide layer 34 overlies the island 16 and an N + type polycrystalline silicon line 36 overlies the silicon dioxide layer 34. The purpose of the N type region 32 is to provide a reliable conductive path between the N + regions 28, 30.
Typically, the integrated circuit 10 is manufactured using a self-aligned technique in which the polycrystalline silicon line 26 is doped to P + type conductivity by ion implantation at the same time that the P + regions 18 and 20 are doped to a P + conductivity. Similarly, the N + doped polycrystalline silicon line 36 is doped in the same ion implantation step that dopes the regions 28, 30 to N + conductivity. Therefore, it has been necessary to dope the P type region 22 and the N type region 32 in separate steps which each required separate photomasks.
In view of the fact that the yield in a semiconductor manufacturing process declines as the number of processing steps increases, the elimination of a photomask step is highly desirable. Accordingly, the present invention is desirable in that it eliminates at least one photomask step in the fabrication of the "universal crossunder" which is the subject of the present invention.
Referring now to Fig. 2, a portion of a semiconductor integrated circuit 100 employing the present invention is shown. The integrated circuit structure 100 comprises an insulating substrate 38 upon which single crystal semiconductor islands 40, 42 are formed.
In the preferred embodiment of the invention, the insulating substrate 38 is comprised of sapphire and the semiconductor islands 40, 42 are comprised of silicon. The semiconductor island 40 comprises a pair of P + regions 44, 46 with a universal crossunder 48 lying therebetween. Overlying the island 42 is a silicon dioxide layer 50. A P + doped polycrystalline silicon line 52 overlies the silicon dioxide layer 50 over the universal crossunder 48. Similarly, the semiconductor island 42 comprises a pair of N + regions 54, 56 having a universal crossunder 58 lying therebetween. A silicon dioxide layer 60 overlies the island 42 and an N + doped polycrystal- line silicon line 62 overlies the silicon dioxide layer 60 over the universal crossunder 58.
The universal crossunders 48, 58 each comprise an N type region 64 which overlies a P type region 66. Accordingly, a conductive path is created between the P + regions 44 and 46 through the P type lower portion 64 of the universal crossunder 48. Similarly, a conductive path between the N + regions 54, 56 is created through the N type upper portion 66 of the universal crossunder 58. The universal crossunders 48, 58 are, accordingly, "universal" in that they may be used to connect either two N + regions or two P + regions.
In order to construct the universal crossunders 66 of the preferred embodiment of the present invention, a slow diffusing N type dopant and a fast diffusing P type dopant are both implanted to approximately the same total dose through a common mask opening.
Following the ion implantation, the dopants are diffused, and they are separated into N and P type layers 64, 66 which are parallel to the surface of the substrate 38 due to their differing diffusion rates.
In a typical example, arsenic is used as the
N type dopant and boron is used as the P type dopant. Both dopants are implanted to a dosage of about 2 x 1014 atoms/cm2 through the oxide layers 50, 60. That doping will result in an ohmic conductor having a sheet resistance low enough to be effectively independent of MOS action. A sheet resistance of less than about 1000 ohms/square, corresponding to an impurity concentration of about 1018 atoms/cm3 is considered to be the maximum sheet resistance which is useful to make a conductor ohmic and effectively independent of MOS action.The silicon epitaxial islands 40, 42 typically have a thickness on the order of 6000A. Following the ion implantation, the remaining steps in the processing of the integrated circuit 100 are equivalent to a 50 minute diffusion at 1050 C. The effect of that diffusion is the creation of the N region 64 over the P region 66 to create the universal crossunders 48, 58.
While the conductivity of the P + and N + -paths in the crossunders 48, 58 is less than could be obtained from isolated P and N type diffusions, such as regions 22, 32 of Fig. 1, adequately conductive paths are provided by the universal crossunders 48, 58.
While the invention has been reduced to practice with equal implantation dosages for the boron and arsenic, the relative implant dosages of the boron and arsenic can be optimized in order that there will be a conductivity efficiency of approximately 40% for both paths. With the equal implantation dosages heretofore used, the efficiency of the N type arsenic implant path 64 of the universal crossunder 58 has been approximately 55% of that of a single N type region, such as region 32 of Fig. 1. Similarly, the P type boron implant 66 of the crossunder 48 has had an efficiency of about 33% of the efficiency of the single P type region 22 of Fig. 1.
Referring now to Figs. 3 and 4, the effects of ion implanting boron and arsenic at implantation energies of about 150 KeV to total dosages of 2 x 1014 atoms/cm2 of each dopant followed by a diffusion of 50 minutes at 1050 C is shown. In Fig. 3, the physical appearance of a universal crossunder 70 during manufacture of a device is shown. The crossunder 70 is formed by ion implanting boron and arsenic (as shown by the arrows in
Fig. 3) through a silicon dioxide layer 72 having a thickness of about 1000 The ion implantation is masked by a defined photoresist layer 74. At this point in the processing the drains and sources have not yet been formed.
Following the diffusion of the implanted ions, the crossunder 70 would have an N type layer 76 which is relatively shallow and an underlying P type layer 78 which extends down to the sapphire substrate 80 in the Nlayer 82 if no drains or sources (as shown in
Fig. 2) were formed. As a result of the diffusion, the P type boron ions tend to diffuse both deeper and over a wider area than the N type arsenic ions. In actual practice the regions on either side of the crossunder 70, which the crossunder 70 is designed to interconnect, would be doped either to N + or
P P + conductivity and the resulting structure, after diffusion, would look like one of the structures shown in Fig. 2, i.e. the N region 76 would not be isolated by the P region 78 from the adjacent regions.
Referring now to Fig. 4, -the results of the diffusion of the ions in forming the universal crossunder 70 of Fig. 3 are shown graphically. In particular, the concentration of arsenic ions is substantially greater than the concentration of boron ions near the surface of the epitaxial silicon layer. Similarly, the concentration of boron ions exceeds the concentration of arsenic ions at a depth of approximately 2000A, and remains higher than the concentration of arsenic ions down to the surface of the sapphire substrate.
The experimental results obtained by the inventor compare well to calculated values of resistance for a crossunder having a width of about 10 microns. In particular, the N type path has a measured resistivity of 600 ohms/square as compared to a calculated resistivity of 780 ohms/square, and the P type path has a measured resistivity of about 200 ohms/square as compared to a calcu lated resistivity of 220 ohms/square.
It should be noted that the utility of the universal crossunders described herein is greatest in applications in which a semiconducting body overlies an insulating substrate.
Accordingly, the CMOS/SOS technology is a perfect application for the universal crossunder, although it may be used in some bulk silicon processes, i.e. where one of the diffusions to be connected is at the power supply potential.
Claims (14)
1. An improved crossunder for integrated circuit devices comprising: a layer of single crystal semiconductor material; a pair of spaced regions of the same conductivity type formed in said semiconductor layer; and a portion of said semiconductor layer lying between said pair of spaced regions, said portion being comprised of a first layer of one conductivity type and a second layer overlying said first layer, said second layer being opposite in conductivity type to said first layer, whereby one of said layers of said portion ohmically connects said pair of spaced regions together, independently of MOS action.
2. An improved crossunder as defined in
Claim 1 wherein said layer of semiconductor material is an epitaxial layer formed on an insulating substrate and in which the conductivity type of each of said spaced regions is uniform throughout said layer.
3. An improved crossunder as defined in
Claim 1 wherein said insulating substrate is comprised of sapphire and said semiconductor material is comprised of silicon.
4. An improved crossunder as defined in
Claim 3 wherein said first layer is P type and said second layer is N type.
5. An improved crossunder as defined in
Claim 4 wherein said first layer is doped with a fast diffusing P type dopant.
6. An improved crossunder as defined in
Claim 5 wherein said P type dopant is boron.
7. An improved crossunder as defined in
Claim 4 wherein said second layer is doped with a slow diffusing N type dopant.
8. An improved crossunder as defined in
Claim 7 wherein said N type dopant is arsenic.
9. An improved method of forming a cross- under for integrated circuits manufactured in single crystalline layers comprising the steps of forming a pair of spaced regions of the same conductivity type in a single crystal semiconductor layer; forming a masking layer over the surface of said semiconductor layer; defining openings in said masking layer over the space between said spaced regions; introducing two different impurities into said semiconductor layer, one of said impurities being of one conductivity type and the other of said impurities being of opposite conductivity type.
10. A method as defined in Claim 9 wherein said one of said impurities is a slow diffusing impurity and the other of said impurities is a fast diffusing impurity.
11. A method as defined in Claim 10 wherein said step of introducing impurities is accomplished by ion implantation.
12. A method as defined in Claim 10 wherein said fast diffusing impurity is boron and said slow diffusing impurity is arsenic.
1 3. An improved crossunder for integrated circuit devices substantially as described with reference to the accompanying drawings.
14. An improved method of forming a crossunder for integrated circuits substantially as described.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US6814879A | 1979-08-20 | 1979-08-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2056771A true GB2056771A (en) | 1981-03-18 |
| GB2056771B GB2056771B (en) | 1983-10-19 |
Family
ID=22080712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8025630A Expired GB2056771B (en) | 1979-08-20 | 1980-08-06 | Crossunders for high density cmos/soj integrated circuits |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5632770A (en) |
| DE (1) | DE3030753A1 (en) |
| FR (1) | FR2463977A1 (en) |
| GB (1) | GB2056771B (en) |
| IT (1) | IT1131790B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997029515A2 (en) * | 1996-02-09 | 1997-08-14 | Siemens Aktiengesellschaft | Separable connecting bridge (fuse) and connectable line interruption (anti-fuse) and process for producing and activating a fuse and an anti-fuse |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3138950A1 (en) * | 1981-09-30 | 1983-04-14 | Siemens AG, 1000 Berlin und 8000 München | Integrated semi-conductor memory |
| JPS61127174A (en) * | 1984-11-26 | 1986-06-14 | Toshiba Corp | Manufacture of semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3443176A (en) * | 1966-03-31 | 1969-05-06 | Ibm | Low resistivity semiconductor underpass connector and fabrication method therefor |
| US3958266A (en) * | 1974-04-19 | 1976-05-18 | Rca Corporation | Deep depletion insulated gate field effect transistors |
| CA1040321A (en) * | 1974-07-23 | 1978-10-10 | Alfred C. Ipri | Polycrystalline silicon resistive device for integrated circuits and method for making same |
| JPS52139388A (en) * | 1976-05-17 | 1977-11-21 | Matsushita Electric Ind Co Ltd | Mos type semiconductor device |
-
1980
- 1980-07-30 IT IT23809/80A patent/IT1131790B/en active
- 1980-08-06 GB GB8025630A patent/GB2056771B/en not_active Expired
- 1980-08-14 JP JP11227380A patent/JPS5632770A/en active Granted
- 1980-08-14 DE DE19803030753 patent/DE3030753A1/en not_active Withdrawn
- 1980-08-19 FR FR8018154A patent/FR2463977A1/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997029515A2 (en) * | 1996-02-09 | 1997-08-14 | Siemens Aktiengesellschaft | Separable connecting bridge (fuse) and connectable line interruption (anti-fuse) and process for producing and activating a fuse and an anti-fuse |
| WO1997029515A3 (en) * | 1996-02-09 | 1997-09-18 | Siemens Ag | Separable connecting bridge (fuse) and connectable line interruption (anti-fuse) and process for producing and activating a fuse and an anti-fuse |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2463977A1 (en) | 1981-02-27 |
| JPH0478011B2 (en) | 1992-12-10 |
| JPS5632770A (en) | 1981-04-02 |
| IT1131790B (en) | 1986-06-25 |
| GB2056771B (en) | 1983-10-19 |
| IT8023809A0 (en) | 1980-07-30 |
| FR2463977B1 (en) | 1983-02-04 |
| DE3030753A1 (en) | 1981-03-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |