JPH0473297B2 - - Google Patents

Info

Publication number
JPH0473297B2
JPH0473297B2 JP58083187A JP8318783A JPH0473297B2 JP H0473297 B2 JPH0473297 B2 JP H0473297B2 JP 58083187 A JP58083187 A JP 58083187A JP 8318783 A JP8318783 A JP 8318783A JP H0473297 B2 JPH0473297 B2 JP H0473297B2
Authority
JP
Japan
Prior art keywords
semiconductor device
external electrode
package
mold layer
resin mold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58083187A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59208755A (ja
Inventor
Katsuhiko Akyama
Juji Kajama
Tetsuo Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP58083187A priority Critical patent/JPS59208755A/ja
Publication of JPS59208755A publication Critical patent/JPS59208755A/ja
Publication of JPH0473297B2 publication Critical patent/JPH0473297B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP58083187A 1983-05-12 1983-05-12 半導体装置のパツケ−ジ及びその製造方法 Granted JPS59208755A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58083187A JPS59208755A (ja) 1983-05-12 1983-05-12 半導体装置のパツケ−ジ及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58083187A JPS59208755A (ja) 1983-05-12 1983-05-12 半導体装置のパツケ−ジ及びその製造方法

Publications (2)

Publication Number Publication Date
JPS59208755A JPS59208755A (ja) 1984-11-27
JPH0473297B2 true JPH0473297B2 (enExample) 1992-11-20

Family

ID=13795315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58083187A Granted JPS59208755A (ja) 1983-05-12 1983-05-12 半導体装置のパツケ−ジ及びその製造方法

Country Status (1)

Country Link
JP (1) JPS59208755A (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62131449U (enExample) * 1986-02-13 1987-08-19
JPH0421320Y2 (enExample) * 1986-02-14 1992-05-15
JPS63301531A (ja) * 1987-06-01 1988-12-08 Nec Corp 混成集積回路装置
JPH08148603A (ja) * 1994-11-22 1996-06-07 Nec Kyushu Ltd ボールグリッドアレイ型半導体装置およびその製造方法
US6329711B1 (en) 1995-11-08 2001-12-11 Fujitsu Limited Semiconductor device and mounting structure
JP3129169B2 (ja) * 1995-11-08 2001-01-29 富士通株式会社 半導体装置及びその製造方法
US5977613A (en) * 1996-03-07 1999-11-02 Matsushita Electronics Corporation Electronic component, method for making the same, and lead frame and mold assembly for use therein
DE10063041B4 (de) 2000-12-18 2012-12-06 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Leadless-Gehäuse-Schaltung und integrierte Leadless-Gehäuse-Schaltung
JP4611569B2 (ja) * 2001-05-30 2011-01-12 ルネサスエレクトロニクス株式会社 リードフレーム及び半導体装置の製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921047A (ja) * 1982-07-27 1984-02-02 Fuji Xerox Co Ltd リ−ドレスチツプキヤリア

Also Published As

Publication number Publication date
JPS59208755A (ja) 1984-11-27

Similar Documents

Publication Publication Date Title
US5198964A (en) Packaged semiconductor device and electronic device module including same
US6911353B2 (en) Semiconductor device and method of manufacturing same
US6246115B1 (en) Semiconductor package having a heat sink with an exposed surface
CN100490140C (zh) 双规引线框
JPH0447977B2 (enExample)
JPH09252065A (ja) 半導体装置及びその製造方法及び基板フレーム
EP0704898A2 (en) Carrier film
US5844779A (en) Semiconductor package, and semiconductor device using the same
JP5169964B2 (ja) モールドパッケージの実装構造および実装方法
CN115132588A (zh) 将电源端子连接到半导体封装内的衬底的方法
JPH0473297B2 (enExample)
US7646089B2 (en) Semiconductor package, method for manufacturing a semiconductor package, an electronic device, method for manufacturing an electronic device
TWI274406B (en) Dual gauge leadframe
US11081428B2 (en) Electronic device with three dimensional thermal pad
JP2819282B2 (ja) 半導体パッケージおよびその製造方法
KR101008534B1 (ko) 전력용 반도체모듈패키지 및 그 제조방법
JPH06132441A (ja) 樹脂封止型半導体装置及びその製造方法
JP2002100710A (ja) 半導体装置および半導体装置の製造方法
JP3398580B2 (ja) 半導体装置の製造方法及び基板フレーム
JP3210503B2 (ja) マルチチップモジュールおよびその製造方法
JPH06342873A (ja) 半導体装置の製造方法
JP3287327B2 (ja) 半導体樹脂封止パッケージの製造方法
JPH06177275A (ja) 放熱性プラスチックｉｃチップキャリア
JP2504262Y2 (ja) 半導体モジュ―ル
JPH09298262A (ja) 半導体装置およびその製造方法