JPH0472319B2 - - Google Patents

Info

Publication number
JPH0472319B2
JPH0472319B2 JP62038934A JP3893487A JPH0472319B2 JP H0472319 B2 JPH0472319 B2 JP H0472319B2 JP 62038934 A JP62038934 A JP 62038934A JP 3893487 A JP3893487 A JP 3893487A JP H0472319 B2 JPH0472319 B2 JP H0472319B2
Authority
JP
Japan
Prior art keywords
word line
enable
circuit
memory
row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62038934A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63205891A (ja
Inventor
Yutaka Takasuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62038934A priority Critical patent/JPS63205891A/ja
Publication of JPS63205891A publication Critical patent/JPS63205891A/ja
Publication of JPH0472319B2 publication Critical patent/JPH0472319B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
JP62038934A 1987-02-20 1987-02-20 メモリ回路 Granted JPS63205891A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62038934A JPS63205891A (ja) 1987-02-20 1987-02-20 メモリ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62038934A JPS63205891A (ja) 1987-02-20 1987-02-20 メモリ回路

Publications (2)

Publication Number Publication Date
JPS63205891A JPS63205891A (ja) 1988-08-25
JPH0472319B2 true JPH0472319B2 (cs) 1992-11-17

Family

ID=12539054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62038934A Granted JPS63205891A (ja) 1987-02-20 1987-02-20 メモリ回路

Country Status (1)

Country Link
JP (1) JPS63205891A (cs)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0229997A (ja) * 1988-07-18 1990-01-31 Sanyo Electric Co Ltd 半導体メモリ及びそれを設けた１チップマイクロコンピュータ

Also Published As

Publication number Publication date
JPS63205891A (ja) 1988-08-25

Similar Documents

Publication Publication Date Title
US6522163B1 (en) Apparatus and method for coupling a first node to a second node using switches which are selectively clocked for fast switching times
JPH054757B2 (cs)
JPS5951072B2 (ja) 半導体メモリ装置
US20040125683A1 (en) Semiconductor integrated circuit device
JPS63188887A (ja) 半導体メモリ
US4131951A (en) High speed complementary MOS memory
KR0155986B1 (ko) 반도체 기억장치
JPH0447397B2 (cs)
JPS6043295A (ja) 半導体記憶装置
JPH0472319B2 (cs)
US4802126A (en) Semiconductor memory device
JPH0263277B2 (cs)
JPH01169798A (ja) 半導体記憶装置
JPH0770224B2 (ja) 同期式スタティックランダムアクセスメモリ
JPH0551997B2 (cs)
JPS6215955B2 (cs)
EP1677309A2 (en) Memory device
JP2702265B2 (ja) 半導体記憶装置
KR100232814B1 (ko) 반도체 메모리
JPH04229482A (ja) Ｄｒａｍメモリ・システム
JPS5846795B2 (ja) 半導体記憶回路
JP2539593B2 (ja) 半導体メモリ回路
JP2665040B2 (ja) 非同期式メモリ回路
JPS61242392A (ja) ダイナミツク型ｒａｍ
JPS6310517B2 (cs)

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees